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Created date
FreeBSD Fix
!3559
· created
Jan 24, 2020
by
Emmanuel Vadot
master
i965
iris
meson
util
Merged
27
updated
Feb 13, 2021
intel: Allow CCS_E on more formats
!3554
· created
Jan 24, 2020
by
Faith Ekstrand
master
ANV
ISL
blorp
i965
iris
Merged
1
updated
Jan 25, 2020
anv+iris+i965: handle platforms without a HW detiler
!3497
· created
Jan 21, 2020
by
Eric Engestrom
master
ANV
i965
iris
Closed
18
updated
Feb 02, 2020
intel/compiler: Fix array bounds warning on GCC 10.
!3491
· created
Jan 21, 2020
by
Timur Kristóf
master
i965
iris
Merged
3
updated
Jan 22, 2020
iris,anv: Properly set the URB deref block size on Gen12
!3454
· created
Jan 17, 2020
by
Faith Ekstrand
Mesa 20.0 Branchpoint
master
ANV
blorp
i965
iris
Merged
23
updated
Feb 03, 2020
intel/compiler: Fix illegal mutation in get_nir_image_intrinsic_image
!3404
· created
Jan 15, 2020
by
Kenneth Graunke
master
i965
Merged
3
updated
Jan 28, 2020
Move the aux transition state machine code to ISL
!3394
· created
Jan 14, 2020
by
Faith Ekstrand
master
ISL
i965
iris
Closed
3
updated
Mar 31, 2020
nir: Add NIR debug passes and MESA_NIR_DBG env variable to enable them
!3390
· created
Jan 14, 2020
by
Danylo Piliaiev
master
ACO
ANV
NIR
RADV
etnaviv
i965
ir3
iris
lima
nouveau
panfrost
radeonsi
vc4
Closed
25
updated
Sep 22, 2020
intel: Update brand strings to match Windows
!3371
· created
Jan 13, 2020
by
Kenneth Graunke
master
ANV
i965
iris
Merged
12
updated
Jan 15, 2020
glsl, nir: Make image_format a pipe_format instead of a GL enum
!3355
· created
Jan 10, 2020
by
Emma Anholt
master
GLSL
ISL
NIR
SPIR-V
freedreno
i965
nouveau
v3d
Merged
21
updated
Feb 05, 2020
WIP: intel: Allow CCS_E on R11G11B10_FLOAT
!3349
· created
Jan 10, 2020
by
Faith Ekstrand
ANV
ISL
blorp
i965
iris
7
updated
Jun 09, 2023
mesa: create program resource hash in a single place
!3313
· created
Jan 08, 2020
by
Tapani Pälli
master
i965
mesa
Merged
3
updated
Dec 26, 2020
type_size sanity
!3297
· created
Jan 06, 2020
by
Emma Anholt
master
GLSL
NIR
gallium
i965
Merged
7
updated
Jan 15, 2020
i965: Create internal front buffer if dri doesn't supply one
!3272
· created
Jan 03, 2020
by
Danylo Piliaiev
i965
Closed
2
updated
Nov 02, 2022
intel: Drop Gen11 WaBTPPrefetchDisable workaround
!3250
· created
Jan 02, 2020
by
Kenneth Graunke
master
ANV
i965
iris
Merged
3
updated
Jan 03, 2020
mesa: Reordering lowered atomics relative to SSBOs
!3240
· created
Dec 31, 2019
by
Emma Anholt
master
NIR
freedreno
gallium
i965
mesa
turnip
Merged
14
updated
Jan 28, 2020
i965: Do not generate D16 B5G6R5_UNORM configs on gen < 8
!3206
· created
Dec 24, 2019
by
Danylo Piliaiev
master
i965
Merged
11
updated
Feb 20, 2020
intel: add driver identifier BO
!3203
· created
Dec 24, 2019
by
Lionel Landwerlin
master
ANV
i965
iris
Merged
22
updated
May 20, 2020
intel: limit shader geometry on BDW GT1
!3173
· created
Dec 19, 2019
by
Lionel Landwerlin
master
ANV
i965
iris
Merged
0
updated
Jan 19, 2021
WIP: intel/urb: fix allocation on Gen8-10 GT1
!3166
· created
Dec 19, 2019
by
Lionel Landwerlin
master
ANV
i965
iris
Closed
5
updated
Apr 13, 2020
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