Commits on Source (76)
-
Alejandro Piñeiro authored
Header is defined at vkGetPipelineCacheData spec, in any vulkan version, and anv, tu and radv were using the same struct, and v3dv was about to do the same. Defining the same struct four times seemed odd, so let's define on a common place. Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Acked-by:
Jonathan Marek <jonathan@marek.ca> Part-of: <!6058>
62bfc700 -
Marcin Ślusarz authored
Found by Coverity. Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Fixes: ef5266eb ("util/os_socket: Add socket related functions.") Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!6067>
eac0ba7f -
Marcin Ślusarz authored
Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!6067>
59bb0ff9 -
Marcin Ślusarz authored
Found by Coverity. Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Fixes: f8f14130 ("util/u_process: add util_get_process_exec_path") Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!6067>
f13042ec -
Marcin Ślusarz authored
Avoids copying random garbage from the stack. Found by Coverity. Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!6067>
28f25853 -
Marcin Ślusarz authored
ColorDrawBuffer is an array of MAX_DRAW_BUFFERS == 8. Found by Coverity. Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Fixes: 7534c536 ("mesa: add EXT_dsa (Named)Framebuffer functions") Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!6067>
0906d5d5 -
Marcin Ślusarz authored
Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!6067>
c3a251f2 -
Marcin Ślusarz authored
Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <!6067>
56228b03 -
Marcin Ślusarz authored
NIR_MAX_VEC_COMPONENTS was bumped from 4 to 16 in a8ec4082 (2019.03.09, merged 2019.12.21) float[4] array was added in acd7796a (2019.06.11, merged 2019.07.11) Found by Coverity. Closes: #3014 Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Fixes: a8ec4082 ("nir+vtn: vec8+vec16 support") Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <!6067>
cb19fe24 -
Tomeu Vizoso authored
After a trace succeeds, check if the rendered image already exists in the repository of reference images, and upload it if it doesn't. This image will be used for comparing with failed retraces. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Daniel Stone <daniels@collabora.com> Part-of: <!6113>
bea34a08 -
Tomeu Vizoso authored
Developers can see how the rendering differed from the executed value. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Daniel Stone <daniels@collabora.com> Part-of: <!6113>
3120b4dc -
Emma Anholt authored
Connor recently ran into an issue where the chezas were hanging where his GPUs weren't, and was blocked on getting some feedback on what was happening. A devcoredump will help non-cheza-having devs debug (or hopefully with other intermittent fails). Closes: #3187 Reviewed-by:
Rob Clark <robdclark@chromium.org> Part-of: <!6036>
cb822745 -
Tomeu Vizoso authored
As these credentials are valid only for 15 minutes, generate them closer to when they are going to be used. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Daniel Stone <daniels@collabora.com> Part-of: <!6124>
e933ac21 -
Boris Brezillon authored
We are about to add support for casts when calculating offset, but let's first turn the if()/else if()/else block into a switch() statement to ease addition of new cases. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <!5682>
6a138239 -
Boris Brezillon authored
Allow casts in a deref chain so we can calculate an offset from a base pointer dereference or have pointer type casts in the middle of the chain (both are pretty common in CL). Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <!5682>
dd155aef -
Rhys Perry authored
And add some "tests" to test and document currently unused features of the framework. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Acked-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by:
Daniel Schürmann <daniel@schuermann.dev> Acked-by:
Timur Kristóf <timur.kristof@gmail.com> Part-of: <!3521>
e6366f90 -
Rhys Perry authored
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Acked-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by:
Daniel Schürmann <daniel@schuermann.dev> Acked-by:
Timur Kristóf <timur.kristof@gmail.com> Part-of: <!3521>
bb7d7755 -
Rhys Perry authored
And add some simple tests to demonstrate/test the pipeline builder and glsl_scraper.py. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Acked-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by:
Daniel Schürmann <daniel@schuermann.dev> Acked-by:
Timur Kristóf <timur.kristof@gmail.com> Part-of: <!3521>
d488d0fd -
Rhys Perry authored
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by:
Daniel Schürmann <daniel@schuermann.dev> Acked-by:
Timur Kristóf <timur.kristof@gmail.com> Part-of: <!3521>
54394a4d -
Rhys Perry authored
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Acked-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by:
Daniel Schürmann <daniel@schuermann.dev> Acked-by:
Timur Kristóf <timur.kristof@gmail.com> Part-of: <!3521>
000530ea -
Daniel Schürmann authored
Acked-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by:
Daniel Schürmann <daniel@schuermann.dev> Acked-by:
Timur Kristóf <timur.kristof@gmail.com> Part-of: <!3521>
f1f9fdb8 -
Boris Brezillon authored
We're trying to get rid of the options argument passed to nir_lower_int64() and use the nir_options.lower_int64_options instead. But before we can do that we must patch nir_lower_int64() callers that don't have this field properly set. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Rob Clark <robdclark@chromium.org> Acked-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <!5588>
9e239259 -
Boris Brezillon authored
This information is exposed through shader->options->lower_int64_options. Removing the extra arg forces drivers to initialize this field correctly. This also allows us to check the int64 lowering options from each int64 lowering helper and decide if we should lower the instructions we introduce. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Matt Turner <mattst88@gmail.com> Reviewed-by:
Rob Clark <robdclark@chromium.org> Acked-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <!5588>
bfee35b4 -
Boris Brezillon authored
That's an attempt at replacing the complex __int64_to_float() and __float_to_int64() implementations found in float64.glsl by a simpler native NIR equivalent. Thanks to that, we can have lower those conversion without having to compile a GLSL shader, which would be quite annoying for OpenCL kernels. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Matt Turner <mattst88@gmail.com> Acked-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <!5588>
936c58c8 -
Boris Brezillon authored
That's more future proof than setting each bit manually. Looks like we already miss nir_lower_ufind_msb64 because of that. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Matt Turner <mattst88@gmail.com> Acked-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <!5588>
025988f8 -
Boris Brezillon authored
Those are now handled by nir_lower_int64() which has native NIR implementations. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Matt Turner <mattst88@gmail.com> Acked-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <!5588>
e1b11486 -
maurossi authored
Fixes the following building error: external/mesa/src/amd/vulkan/radv_android.c:28:10: fatal error: 'vndk/hardware_buffer.h' file not found ^~~~~~~~~~~~~~~~~~~~~~~~ (v2) use the existing preprocessor condition #if ANDROID_API_LEVEL >= 26 Fixes: f36b5274 "radv/android: Add android hardware buffer queries." Reported-and-tested-by:
youling 257 <youling257@gmail.com> Signed-off-by:
Mauro Rossi <issor.oruam@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!6051>
80c135e6 -
Rhys Perry authored
We only need one s_bfe for a conversion with a swizzled source. shader-db (parallel-rdp, Navi): Totals from 487 (71.30% of 683) affected shaders: SpillSGPRs: 3284 -> 3233 (-1.55%); split: -2.71%, +1.16% SpillVGPRs: 2174 -> 2150 (-1.10%); split: -1.24%, +0.14% CodeSize: 2497864 -> 2445544 (-2.09%); split: -2.11%, +0.01% Instrs: 450613 -> 445104 (-1.22%); split: -1.27%, +0.05% Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <!5259>
75a68eee -
Roman Stratiienko authored
Signed-off-by:
Roman Stratiienko <r.stratiienko@gmail.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!6109>
a58081f9 -
Mike Blumenkrantz authored
this is pretty gross, but we need to map the indirect buffer to get the index info and then use that for mapping the index buffer and translating the restart index Reviewed-by:
Dave Airlie <airlied@redhat.com> Acked-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5886>
c77a414e -
Emma Anholt authored
I had this as abort() in my original implementation since I was doing drm-shim and my kernel driver in parallel based around using a SW simulator, and I wanted to always update both, but it means that people's new feature detection code can easily end up breaing their drm-shim shader-db runs (such as intel's kernel_has_dynamic_config_support() checking for -ENOENT instead of -EINVAL for a feature, which showed up on my personal runner but not fd.o's for reasons I'm unclear on). Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <!5994>
75b1f3d3 -
Italo Nicola authored
We were incorrectly assuming uint32 for src_type[1] regardless of src_type[0]. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
b1b0ce04 -
Italo Nicola authored
In the next commits we will be removing the `alu` field from midgard_instruction in order to simplify the code. effective_writemask() doesn't actually use `alu` for anything, it only needs to know the opcode. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
598527f2 -
Italo Nicola authored
In an effort to simplify MIR by not prepacking instructions, this commit removes references to `ins->alu.op` so that we can later remove the `ins->alu` field from midgard_instruction. Every place that was using ins->op was changed to now use the generic `ins->op` field instead. We then reconstruct the `alu.op` field right before emission. This new field is generic and can contain opcodes for ALU, texture or load/store instructions. It should be used in conjunction with `ins->type`, just like the current prepacked `op` field. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
f4c89bf9 -
Italo Nicola authored
In an effort to simplify MIR by not prepacking instructions, this commit removes references to `ins->alu.reg_mode` so that we can later remove the `ins->alu` field from midgard_instruction. Every place that was using reg_mode was changed to now use the generic `ins->src_type` field instead. We then reconstruct the reg_mode field right before emission. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
5f7e0185 -
Italo Nicola authored
Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
f34815c6 -
Italo Nicola authored
In an effort to simplify MIR by not prepacking instructions, this commit removes references to `ins->alu.outmod` so that we can later remove the `ins->alu` field from midgard_instruction. Every place that was using `ins->alu.outmod` was changed to now use the generic `ins->outmod` field instead. We then reconstruct the outmod field right before emission. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!5933>
5011373e -
Italo Nicola authored
Texture instructions in midgard support float outmods, this commit makes it so these instructions are emitted when the conditions are met. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!5933>
83592de7 -
Italo Nicola authored
This commit makes the `ins->op` the correct field to use with texture instructions. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
92c808cd -
Italo Nicola authored
This commit makes `ins->op` the correct field to use with load_store instructions. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
bea6a652 -
Italo Nicola authored
This commit moves the packing of registers and other things from install_registers_instr() to midgard_emit.c, right before emitting the binary. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
1a4d1656 -
Italo Nicola authored
midgard_print.c requires mir_pack_mod to remove references to ins->alu. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
5299239c -
Italo Nicola authored
This commit removes the `ins->alu` field from midgard_instruction, simplifying the code by just recreating midgard_vector_alu later when we have to emit it. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
0f0f9ee7 -
Italo Nicola authored
This refactor prepares emit_alu_bundle() for the next commit that reconstructs branch instructions right before emission. It also simplifies the code since the previous control flow was only better when we had the prepacked fields in midgard_instruction. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
140185eb -
Italo Nicola authored
Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
8150c1d6 -
Italo Nicola authored
Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5933>
3d4deb65 -
Eric Engestrom authored
Signed-off-by:
Eric Engestrom <eric@engestrom.ch> Reviewed-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Part-of: <!6037>
d24e3ea8 -
Eric Engestrom authored
Signed-off-by:
Eric Engestrom <eric@engestrom.ch> Reviewed-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Part-of: <!6037>
f91851e6 -
Eric Engestrom authored
The one caller only ever checks if the return value is NULL or not, so let's simplify the function by only returning that information. Signed-off-by:
Eric Engestrom <eric@engestrom.ch> Reviewed-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Part-of: <!6037>
a77050c0 -
Eric Engestrom authored
Signed-off-by:
Eric Engestrom <eric@engestrom.ch> Reviewed-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Part-of: <!6037>
6d6b82a1 -
Eric Engestrom authored
... and fix the comment to better reflect what this really does. The whole "match a driver at runtime" thing has been gone for years. Signed-off-by:
Eric Engestrom <eric@engestrom.ch> Reviewed-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Part-of: <!6037>
ed3f1e04 -
Eric Engestrom authored
Signed-off-by:
Eric Engestrom <eric@engestrom.ch> Reviewed-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Part-of: <!6037>
258165be -
Lepton Wu authored
Mesa returns a stub function pointer to glAnything for years. Android framework till API level 30 just uses function pointers returned from eglGetProcAddress without checking if the underlying extension is supported. If we return stub pointers for functions in GL_EXT_debug_marker, Android just uses our stub functions instead of its own stubs and then fail the dEQP. In the past, the issue didn't show up because mesa only has limited slots and run out of slots before Android calls eglGetProcAddress on functions inside GL_EXT_debug_marker. Signed-off-by:
Lepton Wu <lepton@chromium.org> Part-of: <!5652>
a2065917 -
Italo Nicola authored
This saves power and time by skipping a roundtrip to the register file. Signed-off-by:
Italo Nicola <italonicola@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!6128>
a91011c9 -
Mike Blumenkrantz authored
Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <!5969>
f3509c07 -
David Stevens authored
This change adds support for BT709 and BT2020 colorspace to the YUV lowering pass. The default remains BT601. This change also fixes minor imprecision in the last digits of the BT601 offsets due to computation from rounded values when the math was simplified. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Rob Clark <robdclark@chromium.org> Part-of: <!6122>
d8fdb8da -
David Stevens authored
Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Rob Clark <robdclark@chromium.org> Part-of: <!6122>
6c11a799 -
Connor Abbott authored
Also document some other registers gleaned from looking at the context switch save/restore routines and fix CP_SDS_REM_SIZE, and make the names line up with the CP perfcntr names. Note that the CP reads the draw stream size in CP_SET_BIN_DATA5 using MEM_READ_ADDR, which is probably why this was mistaken for the draw stream size address. Part-of: <!6123>
8e626879 -
Emma Anholt authored
I'm not the only one doing it, so document it, especially since there's a new trick as of !5669 Reviewed-by:
Andres Gomez <agomez@igalia.com> Part-of: <!5988>
7f40db42 -
Tomeu Vizoso authored
The MinIO server is sometimes complaining about the submitted date being too off. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Daniel Stone <daniels@collabora.com> Part-of: <mesa/mesa!6135>
cf8a8b76 -
Alyssa Rosenzweig authored
Needs a second argument to be consistent with the real IR and the hardware instruction. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Fixes: 8a4efe2d ("pan/bi: Pack second argument of F32_TO_F16") Part-of: <!6142>
aa989aed -
Alyssa Rosenzweig authored
Fixes compile error with -Dtools=panfrost Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Fixes: 946ff9b4 ("bifrost: Add support for nir_op_ishl") Part-of: <!6142>
2dec9092 -
Matt Turner authored
Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
fdfbb1ed -
Matt Turner authored
Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
6809b934 -
Matt Turner authored
It's preferable to require an explicit type. Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
2851c218 -
Matt Turner authored
Produce a brw_reg_type rather than a whole brw_reg and rename a few non-terminals. Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
3e1602cc -
Matt Turner authored
Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
e115c499 -
Matt Turner authored
Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
59801f07 -
Matt Turner authored
Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
3d9c673c -
Matt Turner authored
Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
363e5ef5 -
Matt Turner authored
The next commit fixes a mistake in the assembler and ends up running afoul of this assertion. Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
c883c482 -
Matt Turner authored
Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
af6d6f5c -
Matt Turner authored
brw_reg::subnr is in bytes, like the subnr field in the instruction word, but we disassemble the subregister number in units of the type. For example g0.3<1>F would have a subnr=12. These non-terminals produce a brw_reg and feed into other non-terminals that call brw_reg(), where they are passed the subnr that we set here. brw_reg()'s subnr parameter is expected to be in terms of the register type, and it is multiplied by the type size to calculate the subnr in bytes. In these non-terminals, we don't know the register type yet, so we must store the subregister number as it was given to us in the .subnr field and let the brw_reg() constructor handle the conversion to the canonical byte-based subnr form when it knows the type. Before this patch, subregister numbers applied to these registers would be multiplied with the type size twice. Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
90c18ec8 -
Matt Turner authored
Previously we parsed a src non-terminal but did nothing with it. Since the WAIT instruction is kind of weird, in that you have to give it the same notification subregister for both destination and source, and it always has an exec size of 1, let's parse a destination instead of a source. This way, we can parse a writemask rather than a swizzle in align16 mode, and easily convert the writemask to a swizzle to create the source register. Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
63181df0 -
Matt Turner authored
Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
ac7ecd20 -
Matt Turner authored
Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <!5956>
eaf27eb5
Showing
- .gitlab-ci.yml 2 additions, 1 deletion.gitlab-ci.yml
- .gitlab-ci/bare-metal/capture-devcoredump.sh 14 additions, 0 deletions.gitlab-ci/bare-metal/capture-devcoredump.sh
- .gitlab-ci/bare-metal/init.sh 4 additions, 0 deletions.gitlab-ci/bare-metal/init.sh
- .gitlab-ci/bare-metal/rootfs-setup.sh 2 additions, 0 deletions.gitlab-ci/bare-metal/rootfs-setup.sh
- .gitlab-ci/container/x86_build-base.sh 1 addition, 1 deletion.gitlab-ci/container/x86_build-base.sh
- .gitlab-ci/create-rootfs.sh 1 addition, 0 deletions.gitlab-ci/create-rootfs.sh
- .gitlab-ci/generate_lava.py 0 additions, 4 deletions.gitlab-ci/generate_lava.py
- .gitlab-ci/lava-deqp.yml.jinja2 1 addition, 1 deletion.gitlab-ci/lava-deqp.yml.jinja2
- .gitlab-ci/lava-gitlab-ci.yml 2 additions, 2 deletions.gitlab-ci/lava-gitlab-ci.yml
- .gitlab-ci/lava-tracie.yml.jinja2 1 addition, 1 deletion.gitlab-ci/lava-tracie.yml.jinja2
- .gitlab-ci/prepare-artifacts.sh 1 addition, 4 deletions.gitlab-ci/prepare-artifacts.sh
- .gitlab-ci/tracie-runner-gl.sh 0 additions, 3 deletions.gitlab-ci/tracie-runner-gl.sh
- .gitlab-ci/tracie-runner-vk.sh 0 additions, 3 deletions.gitlab-ci/tracie-runner-vk.sh
- .gitlab-ci/tracie/tracie.py 67 additions, 14 deletions.gitlab-ci/tracie/tracie.py
- docs/ci/index.rst 22 additions, 0 deletionsdocs/ci/index.rst
- meson.build 8 additions, 0 deletionsmeson.build
- meson_options.txt 7 additions, 1 deletionmeson_options.txt
- src/amd/compiler/aco_assembler.cpp 3 additions, 1 deletionsrc/amd/compiler/aco_assembler.cpp
- src/amd/compiler/aco_builder_h.py 1 addition, 1 deletionsrc/amd/compiler/aco_builder_h.py
- src/amd/compiler/aco_instruction_selection.cpp 118 additions, 77 deletionssrc/amd/compiler/aco_instruction_selection.cpp
.gitlab-ci/bare-metal/capture-devcoredump.sh
0 → 100755