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  1. May 05, 2021
  2. May 04, 2021
    • Marek Olšák's avatar
      util: fix (re-enable) L3 cache pinning · 3707ffe7
      Marek Olšák authored and Eric Engestrom's avatar Eric Engestrom committed
      
      cores_per_L3 was uninitialized, so it was always disabled.
      Remove the variable and do it differently.
      
      Fixes: 11d2db17 - util: rework AMD cpu L3 cache affinity code.
      
      Reviewed-by: default avatarDave Airlie <airlied@redhat.com>
      Part-of: <!10526>
      (cherry picked from commit 48d2ac4e)
      3707ffe7
    • Faith Ekstrand's avatar
      intel/nir: Set lower txs with non-zero LOD · 8f8ce535
      Faith Ekstrand authored and Eric Engestrom's avatar Eric Engestrom committed
      
      There's a recently discovered HW bug affecting hardware at least as far
      back as Skylake where, if the LOD is out-of-bounds for any SIMD lane,
      then garbage may be returned in all SIMD lanes.  The easy solution is to
      set lower_txs_lod so that we always have a constant LOD of 0 which we
      know a priori is always in-bounds.  Fortunately, not many shaders
      actually use textureSize() with LOD.
      
      Shader-db results on Ice Lake:
      
          total instructions in shared programs: 19948537 -> 19948564 (<.01%)
          instructions in affected programs: 3859 -> 3886 (0.70%)
          helped: 0
          HURT: 7
      
      One of the shaders is in Civilization: Beyond Earth, and the rest are
      all in Civilization VI.
      
      Reviewed-by: default avatarFrancisco Jerez <currojerez@riseup.net>
      Reviewed-by: default avatarAnuj Phogat <anuj.phogat@gmail.com>
      Cc: mesa-stable@lists.freedesktop.org
      Part-of: <!10538>
      (cherry picked from commit 05a37e24)
      8f8ce535
    • Connor Abbott's avatar
      ir3/postsched: Fix dependencies for a0.x/p0.x · 31836d7f
      Connor Abbott authored and Eric Engestrom's avatar Eric Engestrom committed
      a0.x is written as a half-reg, but just interpreting it as "hr61.x" will
      result in it overlapping with r30.z in merged mode, which is not what
      the hardware does at all. This introduced a spurious dependency on
      a write to r30.z which resulted in an assert tripping. Just pretend it's
      a full reg instead.
      
      This fixes
      spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs
      with the new RA.
      
      Fixes: 0f78c324 ("freedreno/ir3: post-RA sched pass")
      Part-of: <mesa/mesa!10591>
      (cherry picked from commit e597f8b1)
      31836d7f
    • Eric Engestrom's avatar
      .pick_status.json: Update to 1d418e79 · b0f5108c
      Eric Engestrom authored
      b0f5108c
  3. May 03, 2021
  4. May 02, 2021
  5. Apr 30, 2021
  6. Apr 29, 2021
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