radv,ac/llvm: use a dword alignment for descriptor loads
RADV doesn't try to keep anything 16 or 32 byte aligned. RADV also seems to create better code for some reason. fossil-db (Sienna Cichlid): Totals from 37693 (30.93% of 121873) affected shaders: SGPRs: 1762792 -> 1785504 (+1.29%); split: -1.01%, +2.30% VGPRs: 1761032 -> 1760808 (-0.01%); split: -0.09%, +0.07% SpillSGPRs: 55793 -> 56011 (+0.39%); split: -3.49%, +3.88% SpillVGPRs: 16766 -> 16387 (-2.26%); split: -3.99%, +1.73% CodeSize: 82902228 -> 82781608 (-0.15%); split: -0.29%, +0.14% Scratch: 3024896 -> 2987008 (-1.25%); split: -3.08%, +1.83% MaxWaves: 919794 -> 920302 (+0.06%); split: +0.09%, -0.03% shader-db (Sienna Cichlid): Totals from affected shaders: SGPRS: 3976 -> 3976 (0.00 %) VGPRS: 3392 -> 3392 (0.00 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 178792 -> 178980 (0.11 %) bytes Max Waves: 1389 -> 1389 (0.00 %) Signed-off-by:Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Cc: mesa-stable Closes: mesa/mesa#4715 Part-of: <mesa/mesa!10543> (cherry picked from commit d918a59d)