ir3/postsched: Fix dependencies for a0.x/p0.x
a0.x is written as a half-reg, but just interpreting it as "hr61.x" will result in it overlapping with r30.z in merged mode, which is not what the hardware does at all. This introduced a spurious dependency on a write to r30.z which resulted in an assert tripping. Just pretend it's a full reg instead. This fixes spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs with the new RA. Fixes: 0f78c324 ("freedreno/ir3: post-RA sched pass") Part-of: <mesa/mesa!10591> (cherry picked from commit e597f8b1)