Before the commit updating addrlib, sw_D mode couldn't be selected when
ADDR2_GET_PREFERRED_SURF_SETTING_INPUT::flags.display was false (gfx9 only).

Now it only depends on the preferredSwSet value so let's use sw_S = 1 when
the surface doesn't need a sw_D mode.

Fixes: 69ea473e ("amd/addrlib: update to the latest version")

Fixes: ba10fb3f ("radeonsi: preserve the scanout flag for shared resources on gfx9 and gfx10")

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

It seems less brittle to not assume they are in the same order for src
and dst instructions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

Caught by the sanity checking in nir_intrinsic_copy_const_indices()
(which is introduced by the next patch).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

Cleans up a couple spots that were still open-coding this.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

Kristian Høgsberg authored 4 years ago and Rob Clark committed 4 years ago

These intrinsics are supposed to map to the underlying hardware
instructions, which don't have wrmask. We use them when we lower
store_output in the geometry pipeline and since store_output gets
lowered to temps, we always see full wrmasks there.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <mesa/mesa!5028>

The binning variant likely won't have any UBO load code in it, so we were
writing past constlen (and sometimes asserting about it) when loading more
than one ubo block.

Part-of: <mesa/mesa!5027>

Part-of: <mesa/mesa!5026>

This fixes problems in a number of games, including SuperTuxKart,
OpenMW and RVGL.

v2: Use MALI_READS_ZS | 0x20 instead of MALI_WRITES_Z to match with
the blob. Keep using 0x400 | 0x20 when depth is disabled.

Closes: #2620
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!5001>

Fixes: 34f32a6d
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <mesa/mesa!5025>

While we're here, we add a nice detailed comment about why always
assuming internal is ok.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <mesa/mesa!5022>

It probably doesn't matter because that buffer should have a stride of
zero.  However, it still seems like a good idea just to be safe.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <mesa/mesa!5022>

The remaining two fails in the list are the same as for the normal CI run.

Part-of: <mesa/mesa!4858>

It saves addressing math, but may cause multiple loads to be done and
bcseled due to NIR not giving us good address alignment information
currently.  I don't have any workloads I know of using non-const-uploaded
UBOs, so I don't have perf numbers for it

This makes us match the GLES blob's behavior, and turnip (other than being
bindful).

Part-of: <mesa/mesa!4858>

With the upcoming LDC usage in the GL driver, we don't want to be
uploading descriptors for every UBO when they aren't actually in use.
Trimming NIR's num_ubos will avoid that, and cleans up num_ubo handling
elsewhere right now.

Part-of: <mesa/mesa!4858>

I found that when moving more UBOs to load_ubo_ir3, analyze_ubo_ranges
would move things back in a broken way.  We can just run this pass later
and drop the _ir3 path.

Part-of: <mesa/mesa!4858>

Otherwise, we might end up inserting the nir_intrinsic_load_ubo_ir3()
after the non-offset src's definition, leading to nir_validate() failures.

Part-of: <mesa/mesa!4858>

Just copy the src through.

Part-of: <mesa/mesa!4858>

I keep wanting this number for debugging shaders.

Part-of: <mesa/mesa!4858>

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <mesa/mesa!5019>

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <mesa/mesa!5019>

The vma_heap allocator was originally designed to prefer high addresses
in order to find bugs in ANV's high address handling.  However, there
are cases where you might want the allocator to prefer lower addresses
for some reason.  This provides a configure bit for exactly this
purpose.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <mesa/mesa!5019>

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <mesa/mesa!5019>

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <mesa/mesa!5019>

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <!4898>

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <mesa/mesa!4898>

It's not a required format and it causes issues with some features.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <mesa/mesa!4898>

Per https://android.googlesource.com/platform/frameworks/native/+/master/vulkan/libvulkan/swapchain.cpp#745


the format Android requires is R5G6B5, and we have it backwards here.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <mesa/mesa!4898>

Part-of: <mesa/mesa!5023>

Closes: mesa/mesa#2870


Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <mesa/mesa!4929>

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <mesa/mesa!4929>

Closes: mesa/mesa#2870


Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <mesa/mesa!4929>

Reported by Ian Romanick.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <mesa/mesa!5016>

Part-of: <mesa/mesa!4993>

Enable the tgsi to nir cache for radeonsi.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <mesa/mesa!4993>

A trace of a Hat in Time, which builds thousands of shaders
takes 339 seconds to run the second time without this patch,
and 41 seconds with it (basically there is no more loading times).

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <mesa/mesa!4993>

ttn is slow, let's disk cache it.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <mesa/mesa!4993>