Draft: Intel LNL platform
This MR adds the pci-ids for LNL, bit it also provides an overview/status of LNL upstreaming, similar to MR 18481.
Prerequisites:
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genxml -
!24547 (merged) intel_genxml module -
!24605 (merged) add newline to end of genxml (plus some intel_genxml refactoring for !20593 (merged)) -
!24902 (merged) fix comparing genxml differing in length -
!24903 (merged) fix comparing genxml nodes that have trivial tail whitespace difference -
!20593 (merged) genxml import -
!26390 (merged) COMPUTE_WALKER related changes
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isl -
!25253 (merged) build with Xe2 -
!26593 (merged) Default MOCS for Xe2 -
!26801 (merged) RENDER_SURFACE_STATE -
!27016 (merged) Disable route of Sampler LD message to LSC -
!27113 (merged) introduce ISL_TILING_64_XE2 for Xe2+ platforms
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iris, anvil -
!24746 (merged) 3DSTATE_PRIMITIVE_REPLICATION -
!25411 (merged) build Xe2 code paths into Anvil and Iris -
!26178 (merged) Indirect commands unrolling -
!26421 (merged) Merged partial MR
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!26426 (merged) EXT_depth_range_unrestricted -
!26437 (merged) minSubgroupSize -
!26438 (merged) 3DSTATE_TE changes -
!26444 WIP: Resource Barriers -
!26600 (closed) LNL state programming updates for 3DSTATE_CLEAR_PARAMS, 3DSTATE_WM_HZ_OP, 3DSTATE_VS, 3DSTATE_PS, 3DSTATE_PS_EXTRA, 3DSTATE_GS, 3DSTATE_HS -
!26637 (merged) No need to emit PIPELINE_SELECT on Xe2 -
!27713 (merged) anv: Set timestampValidBits to 64bits -
!27823 (merged) anv: add a command streamer stall on Xe2+ when switching pipelines -
!27983 (merged) anv,blorp: Set COMPUTE_WALKER Message SIMD field -
!28201 (merged) WA 1509820217 is no impact for Xe2+
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compiler -
!25020 (merged) reg_unit(devinfo) -
!25195 (merged) URB -
!25514 (merged) SWSB -
!25506 (merged) ExBSO on UGM -
!26208 (merged) Sparse residency updates -
!26585 (merged) Xe+ multipolygon PS dispatch, required for Xe2 multipolygon dispatch -
!26605 (merged) Removal of SIMD8 shader dispatch modes on Xe2 -
!26606 (merged) Implement fragment shader dispatch on Xe2 -
!26860 (merged) Codegen for Xe2 -
!26886 (merged) intel/fs: Check fs_visitor instance before using it -
!26994 (merged) Small misc changes in intel/compiler -
!26960 (merged) intel/fs: Update invocation id access for Xe2+ -
!27165 (merged) More Xe2 misc in compiler, includes proper codegen of reg/subreg numbers -
!27235 (merged) SIMD16 Math on Xe2+ -
!27305 (merged) texture sampler messages -
!27447 (merged) anv: Implement VK_AMD_texture_gather_bias_lod -
!27458 (merged) intel/compiler: Add texture operation lowering pass -
!27529 (merged) intel/compiler: Compiler changes around nir_intrinsic_load_topology_id_intel -
!27602 (merged) intel/compiler: Xe2+ can do URB load/store with a byte offset -
!27498 (merged) intel/compiler: Fix disassembly of URB message descriptor on Xe2+ -
!28082 (merged) intel/fs: fixup sampler header message on Gfx11+ -
!28110 (merged) FCS terminate -
!28191 (merged) Small changes -
!28279 (merged) Handle Xe2 in opt_zero_samples -
!28283 (!28306 (merged), !28484 (merged)) -
!28404 (merged) Misc compiler fixes. -
!28188 (merged) Compiler scheduler fix -
!28479 2 validation fixes for Xe2 -
!28480 (merged) Wa 22016140776 -
...
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small/misc: -
!24418 (merged) -
!24419 (merged) -
!24421 (merged) -
!26396 (merged) Adjust prefetch_size values for Xe2 engines -
!26403 (merged) Changes around PIPE_CONTROL and PIPELINE_SELECT -
!26639 (merged) Misc fixes for intel compiler on Xe2 -
!26742 (merged) Remove L3ALLOC -
!26837 (merged) Couple of disasm fixes -
!27316 (merged) anv trtt range -
!28833 compression infra -
!28910 preferred slm size
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workarounds -
!26152 (merged) preparation for workaround -
!25897 (merged) Bindless sampler heap issue
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pci-ids -
!25481 INTEL_FORCE_PROBEand initial devinfo/pci -
enable pci-ids (this MR; blocked on kernel and Mesa)
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