Intel LNL platform
This MR adds the pci-ids for LNL, bit it also provides an overview/status of LNL upstreaming, similar to MR 18481.
Prerequisites:
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genxml -
!24547 (merged) intel_genxml module -
!24605 (merged) add newline to end of genxml (plus some intel_genxml refactoring for !20593 (merged)) -
!24902 (merged) fix comparing genxml differing in length -
!24903 (merged) fix comparing genxml nodes that have trivial tail whitespace difference -
!20593 (merged) genxml import -
!26390 (merged) COMPUTE_WALKER related changes -
!29264 (merged) state programming updates
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isl -
!25253 (merged) build with Xe2 -
!26593 (merged) Default MOCS for Xe2 -
!26801 (merged) RENDER_SURFACE_STATE -
!27016 (merged) Disable route of Sampler LD message to LSC -
!27113 (merged) introduce ISL_TILING_64_XE2 for Xe2+ platforms
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iris, anvil -
!24746 (merged) 3DSTATE_PRIMITIVE_REPLICATION -
!25411 (merged) build Xe2 code paths into Anvil and Iris -
!26178 (merged) Indirect commands unrolling -
!26421 (merged) Merged partial MR
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!26426 (merged) EXT_depth_range_unrestricted -
!26437 (merged) minSubgroupSize -
!26438 (merged) 3DSTATE_TE changes -
!26444 Resource Barriers -
!26600 (closed) LNL state programming updates for 3DSTATE_CLEAR_PARAMS, 3DSTATE_WM_HZ_OP, 3DSTATE_VS, 3DSTATE_PS, 3DSTATE_PS_EXTRA, 3DSTATE_GS, 3DSTATE_HS -
!26637 (merged) No need to emit PIPELINE_SELECT on Xe2 -
!27713 (merged) anv: Set timestampValidBits to 64bits -
!27823 (merged) anv: add a command streamer stall on Xe2+ when switching pipelines -
!27983 (merged) anv,blorp: Set COMPUTE_WALKER Message SIMD field -
!28201 (merged) WA 1509820217 is no impact for Xe2+ -
intel/perf: Add performance counter support for... (!29529 - merged) -
!29615 - intel: Enable depth buffer write through for multi sampled images in Xe2 -
!29616 (merged) - intel: Compute walker related changes for Xe2 -
!29617 (merged) - intel: Xe2 Mesh shader related changes -
intel: Changes for TBIMR on Xe2 (!29706) -
!29775 (merged) - anv: fix declaration of memory types -
!29926 (merged) anv: Fix push constant layout on Xe2 platforms. -
!29953 (merged) anv: LNL+ doesn't need the special flush for sparse
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compiler -
!25020 (merged) reg_unit(devinfo) -
!25195 (merged) URB -
!25514 (merged) SWSB -
!25506 (merged) ExBSO on UGM -
!26208 (merged) Sparse residency updates -
!26585 (merged) Xe+ multipolygon PS dispatch, required for Xe2 multipolygon dispatch -
!26605 (merged) Removal of SIMD8 shader dispatch modes on Xe2 -
!26606 (merged) Implement fragment shader dispatch on Xe2 -
!26860 (merged) Codegen for Xe2 -
!26886 (merged) intel/fs: Check fs_visitor instance before using it -
!26994 (merged) Small misc changes in intel/compiler -
!26960 (merged) intel/fs: Update invocation id access for Xe2+ -
!27165 (merged) More Xe2 misc in compiler, includes proper codegen of reg/subreg numbers -
!27235 (merged) SIMD16 Math on Xe2+ -
!27305 (merged) texture sampler messages -
!27447 (merged) anv: Implement VK_AMD_texture_gather_bias_lod -
!27458 (merged) intel/compiler: Add texture operation lowering pass -
!27529 (merged) intel/compiler: Compiler changes around nir_intrinsic_load_topology_id_intel -
!27602 (merged) intel/compiler: Xe2+ can do URB load/store with a byte offset -
!27498 (merged) intel/compiler: Fix disassembly of URB message descriptor on Xe2+ -
!28082 (merged) intel/fs: fixup sampler header message on Gfx11+ -
!28110 (merged) FCS terminate -
!28191 (merged) Small changes -
!28279 (merged) Handle Xe2 in opt_zero_samples -
!28283 (merged) (!28306 (merged), !28484 (merged)) -
!28404 (merged) Misc compiler fixes. -
!28188 (merged) Compiler scheduler fix -
!28479 2 validation fixes for Xe2 -
!28480 (merged) Wa 22016140776 -
intel/brw: update Xe2 max SIMD message sizes (!29212 - merged) -
!29261 extended descriptor updates for Xe2 -
!29271 (merged) intel/compiler: Misc fixes around size_written for Xe2+ -
!29350 (closed) intel/brw/xe2+: Ask driver for PS payload registers based on barycentric load intrinsics in use. -
!29356 (closed) intel/brw: Xe2 TGM and UGM restrict loads of 8 or more to SIMD16 -
Tweaks to iadd3 with int64, small iadd3 opts an... (!29148 - merged) -
intel/compiler: Add indirect mov lowering pass (!29316 - merged) -
intel/compiler: fix shuffle generation on LNL (!29504 - merged) -
!29543 (merged) intel: Fix addressing of shader scratch surfaces for Xe2+ platforms. -
!29271 (merged) intel/fs: Adjust destination register size -
intel/brw: Fix limiting Xe2 to SIMD16 when dual... (!29561) -
!29847 (merged) intel/xe2+: Implement ALU-based pixel interpolation. -
intel/brw: Retype some regs to uint for Xe2 ind... (!29925 - merged) -
...
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small/misc: -
!24418 (merged) -
!24419 (merged) -
!24421 (merged) -
!26396 (merged) Adjust prefetch_size values for Xe2 engines -
!26403 (merged) Changes around PIPE_CONTROL and PIPELINE_SELECT -
!26639 (merged) Misc fixes for intel compiler on Xe2 -
!26742 (merged) Remove L3ALLOC -
!26837 (merged) Couple of disasm fixes -
!27316 (merged) anv trtt range -
!28910 (merged) preferred slm size -
!28190 TR-TT for compute and copy -
!29562 (merged) intel: Assorted changes enabling features newly introduced in Xe2.
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compression -
!28833 (merged) compression infra -
Intel Xe2 Compression - Part 2 (!28620 - merged) (*) -
Intel: Xe2 Compression - MCS Part (!28919 - merged) -
intel/isl: Split Xe2 changes into its own files (!29702 - merged) -
Intel/isl: Support CMF mapping of ISL formats (... (!29905 - merged) -
Xe2 Compression - Part 1 (!29906 - merged) -
intel/common: Ensure SIMD16 for fast clear kern... (!29907 - merged) -
Intel: Disable PAT based compression on tiling X (!29976) -
Intel/vulkan: Disable fast-clear and aux tracki... (!29966 - merged) (*) -
(NEW) Have a new compressed PAT entry to differenciat... (!29928) -
intel/dev: Add documentation around PAT entries... (!29950 - merged)
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workarounds -
!26152 (merged) preparation for workaround -
!25897 (merged) Bindless sampler heap issue -
anv: implement WA 14018283232 (!29297 - merged) -
!29619 (merged) - intel: Implement Xe2 Wa_14019708328 and Wa_14019857787 -
blorp: WA_16021232440 - Disable fastclear when ... (!29182) -
anv: flush the L1 cache on Xe2 after emitting 3... (!30298)
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pci-ids -
mr-25481(in 29273)INTEL_FORCE_PROBEand initial devinfo/pci -
Add INTEL_FORCE_PROBE, initial LNL devinfo and ... (!29273 - merged) -
intel: Silence INTEL_FORCE_PROBE warning during... (!29445 - merged) -
!29457 (merged) Adds BMG, but also updates LNL WA json info -
enable pci-ids (tested with drm-next fb625bf6187d from June 28, 2024) -
!30056 Enable BMG pci-ids
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Edited by Jordan Justen