intel: Second round of compiler patches enabling Xe2 platforms: SWSB synchronization support.
This MR updates the software scoreboarding infrastructure in our compiler backend to support the Xe2 ISA. The SWSB binary encoding is different enough on Xe2 platforms that the encoding/decoding logic needs to be largely rewritten. The changes to the SWSB software scoreboard pass are less dramatic: FP64 and extended math instructions are now handled as in-order EU pipelines, which is more efficient than the out-of-order tracking we had to do in previous generations. FP64 instructions are implemented by the hardware in a special-purpose "long" EU pipeline. Support for 64-bit integer instructions is re-introduced, and is now handled by the standard integer pipeline instead of relying on the long pipeline. The doubled GRF file size requires updating some of the tracking done in the software scoreboard and other compiler passes. Also, the hardware now supports up to 32 SBID tokens, but that isn't enabled by this series, since the additional tokens are only usable in large GRF mode.