Commits on Source (66)
-
Bas Nieuwenhuizen authored
However complicated DCC addressing is it is still based on tiles. If we have the intra-tile offsets + tile dimensions we can expand that to the full image ourselves. Behavior around ~1080p on a 2500U: old: 30-60 ms on every miss new: 5 ms initally (miss in the tile cache) <0.5 ms afterwards The most common case is that the tile cache only contains data for 2 tiles, which for Raven/Renoir/Navi14 will be 4 KiB each, so the size increase is fairly modest. Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5865>
a37aeb12 -
Bas Nieuwenhuizen authored
Cleanup. Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5865>
862d85a6 -
Emma Anholt authored
legalize_block() can get run multiple times, which I didn't notice when adding fine derivs support. Other instruction clones change things such that the legalization won't trigger again, but that didn't apply to the DS.PP legalization. To keep someone else from tripping over this, split the one-shot legalization out of the iterative sync flag application. Fixes failures in dEQP-VK.glsl.derivate.dfdxfine.* Closes: #3198 Part-of: <!5699>
3d7d5d22 -
Emma Anholt authored
Since I was going back to look at fine derivs again, add some tests of instruction encoding. Part-of: <!5699>
5b380483 -
Icecream95 authored
panfrost_bo_wait is often used after panfrost_flush_batches_accessing_bo, so make them take similar arguments for consistency. Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5962>
858cc13e -
Icecream95 authored
The function now takes a bool flush_readers instead of an access type, but some calls were not updated. Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5962>
0ef168d5 -
maurossi authored
Fixes the following build error: In file included from external/mesa/src/panfrost/encoder/pan_blit.c:34: In file included from external/mesa/src/panfrost/encoder/../midgard/midgard_compile.h:27: external/mesa/src/compiler/nir/nir.h:52:10: fatal error: 'nir_opcodes.h' file not found ^~~~~~~~~~~~~~~ 1 error generated. Fixes: 293f2518 ("panfrost: Use Midgard-specific reloads") Signed-off-by:
Mauro Rossi <issor.oruam@gmail.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5961>
9e9c8e2f -
Mike Blumenkrantz authored
there's no sense in having these objects sitting around when they can never be used again requires adding a zink_context* pointer to each program in order to prune the hash table entry Reviewed-by:
Antonio Caggiano <antonio.caggiano@collabora.com> Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <!5887>
7116decf -
Mike Blumenkrantz authored
this is a big leak Reviewed-by:
Antonio Caggiano <antonio.caggiano@collabora.com> Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <!5887>
1ff2d195 -
Mike Blumenkrantz authored
more leaks Reviewed-by:
Antonio Caggiano <antonio.caggiano@collabora.com> Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <!5887>
adc4f389 -
Mike Blumenkrantz authored
these are all fairly large sources of leaks Reviewed-by:
Antonio Caggiano <antonio.caggiano@collabora.com> Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <!5887>
2b343238 -
Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5957>
835201dd -
Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5957>
79b0651c -
Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5957>
0472ca2a -
Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5957>
5be171b8 -
Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5957>
c2d94aa3 -
Rob Clark authored
Print out the assigned vreg names earlier. Also print the few special nodes. Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5957>
6317f7d5 -
Rob Clark authored
We shouldn't divide-by-two for half-reg arrays. We set the proper node interference class, based on `arr->half`. Fixes a RA fail with 16b arrays: src/freedreno/ir3/ir3_ra.c:633: name_to_array: Assertion `!"invalid array name"' failed. Caused by use/def iterators returning `arr->length` vreg namess, but only assigning the array half that many names. Also, since we are assigning unique vreg names to each array element, there is no need to try and convert from half-reg to it's conflicting full reg when pre-coloring the array elements. Getting us closer to having half-arrays work sanely with split-register-file (a5xx and earlier). Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5957>
b1465c38 -
Rob Clark authored
Properly handle the difference between split and merged register file when determining where arrays can fit without conflicting with other arrays or pre-colored instructions. 1) if not mergedregs, only consider other things with same precision as potentially conflicting 2) if mergedregs, calculate everything in therms of half-regs and convert back to fullregs in the end Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5957>
912ad091 -
Dave Airlie authored
Running complete CTS turned up a missing cond render. Fixes KHR-GL45.compute_shader.conditional-dispatching Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <!5944>
0e0b6d47 -
Dave Airlie authored
v1.1: Merge two if blocks (Roland) Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <!5914>
41c7bb6e -
Dave Airlie authored
I hadn't realised these were disabled, llvmpipe now exposes this extension. One additional failure is fine to get the added testing coverage. Reviewed-by:
Michel Dänzer <mdaenzer@redhat.com> Part-of: <!5973>
4708ccbf -
Gert Wollny authored
Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
55cc7129 -
Gert Wollny authored
Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
deccf022 -
Gert Wollny authored
Setting the offset must happen in the same CF like using it, so don't emit ALU instruction between the tex instructions. Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
25861881 -
Gert Wollny authored
Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
aca99e6f -
Gert Wollny authored
Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
d31ef0b7 -
Gert Wollny authored
This makes sure no components are written that shouldn't be written. Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
c18b1c6d -
Gert Wollny authored
Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
2779aa36 -
Gert Wollny authored
Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
05df4bfb -
Gert Wollny authored
The sample mask must be applied when more then one sample is available or multisamplig is not enabled, so add a shader key to track this. Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
c91979c6 -
Gert Wollny authored
This fixes all the piglits from arb_sample_shading "samplemask * *" with the nir backend. Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
3ea847e6 -
Gert Wollny authored
Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <!5963>
21d296a4 -
Gert Wollny authored
Fixes: arb_gpu_shader5-xfb-streams Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <mesa/mesa!5963>
1fa36c1d -
Pierre-Eric Pelloux-Prayer authored
Otherwise we might get VM_L2_PROTECTION_FAULT_STATUS errors. Fixes: 8275dc1e ("ac/surface: fix epitch when modifying surf_pitch") Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5841>
87ecfdfb -
Pierre-Eric Pelloux-Prayer authored
This fix si_compute_copy_image for yuyv image (so using PIPE_FORMAT_R8G8_R8B8_UNORM). With this change, the following gst pipeline produce the expected results for various image sizes (with or without AMD_DEBUG=nodma): gst-launch-1.0 filesrc location=input.jpg ! jpegparse ! vaapijpegdec ! filesink location=output.yuv Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5841>
d2a3ca28 -
Samuel Pitoiset authored
AMDGPU_GEM_CREATE_CPU_GTT_USWC should be faster when CPU reads are unexpected (because they aren't cached). Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!5959>
d1bba2ee -
Samuel Pitoiset authored
When the VRAM size is small and the preferred heap only VRAM, the kernel tries to always honor the requested heap and it does a ton of evictions which is a disaster for performance. On APUs, VRAM and GTT have similar performance, so allow the kernel to choose the best placement (GTT or VRAM) itself. This gives a huge performance boost with Doom Eternal on RAVEN. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!5665>
28c227c7 -
Rhys Perry authored
If the SPIR-V had a shared+image memory barrier, we would emit two NIR barriers: a shared barrier and an image barrier. Unlike a single barrier, two barriers allows transformations such as: intrinsic image_deref_store (ssa_27, ssa_33, ssa_34, ssa_32, ssa_25) (1) intrinsic memory_barrier_shared () () intrinsic memory_barrier_image () () intrinsic store_shared (ssa_35, ssa_24) (0, 1, 4, 0) -> intrinsic memory_barrier_shared () () intrinsic store_shared (ssa_35, ssa_24) (0, 1, 4, 0) intrinsic image_deref_store (ssa_27, ssa_33, ssa_34, ssa_32, ssa_25) (1) intrinsic memory_barrier_image () () This commit fixes two dEQP-VK.memory_model.* CTS tests with ACO. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <!5951>
fac813dc -
For most GPUs RGTC is disabled, so it needs to be emulated, using the fake_rgtc option of u_transfer_helper. Passes the rgtc-teximage tests in piglit. v2: Update docs/features.txt (Alyssa) Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5975>
c1d3d39e -
Icecream95 authored
This will be needed for 8x MRT with 128-bit framebuffer formats. Adds support for 256-bit, 1024-bit, and 2048-bit tilebuffer allocations, depending on the amount of data required. v2: Squash commits (Alyssa) Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5892>
978f963e -
Icecream95 authored
Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5892>
3ec252a3 -
Icecream95 authored
Fixes piglit test fbo-drawbuffers-blend-add when fixed-function blending is disabled in panfrost_get_blend_for_context. Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5892>
e764192f -
Daniel Schürmann authored
This avoids combination with other bcsel operations, and as b2i is often a no-op (when used for iadd and such), the resulting pattern is preferable. Totals from affected shaders: (VEGA) SGPRS: 598448 -> 598448 (0.00 %) VGPRS: 457940 -> 457352 (-0.13 %) Spilled SGPRs: 127154 -> 127154 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 64836352 -> 64802728 (-0.05 %) bytes LDS: 781 -> 781 (0.00 %) blocks Max Waves: 22931 -> 22931 (0.00 %) Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!4830>
de0ebaf0 -
Daniel Schürmann authored
Booleans are often more efficient with register usage. This also allows to move comparisons further. Totals from affected shaders: (VEGA) SGPRS: 451608 -> 450320 (-0.29 %) VGPRS: 351448 -> 351256 (-0.05 %) Spilled SGPRs: 105 -> 105 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 1008 -> 1008 (0.00 %) dwords per thread Code Size: 26555596 -> 26551080 (-0.02 %) bytes LDS: 10323 -> 10323 (0.00 %) blocks Max Waves: 42850 -> 42934 (0.20 %) Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!4830>
e4281dbe -
Daniel Schürmann authored
Found in some Detroit: Become Human shaders. Totals from affected shaders: SGPRS: 700256 -> 700256 (0.00 %) VGPRS: 507208 -> 507212 (0.00 %) Spilled SGPRs: 142531 -> 142531 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 76404616 -> 76301768 (-0.13 %) bytes LDS: 43 -> 43 (0.00 %) blocks Max Waves: 21438 -> 21438 (0.00 %) Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!4830>
8e1b75b3 -
Daniel Schürmann authored
This just reverts fsign/isign lowering. Totals from affected shaders: SGPRS: 257496 -> 256672 (-0.32 %) VGPRS: 181800 -> 178864 (-1.61 %) Spilled SGPRs: 105 -> 105 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 11355852 -> 11141840 (-1.88 %) bytes LDS: 3789 -> 3789 (0.00 %) blocks Max Waves: 30453 -> 30951 (1.64 %) Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!4830>
2fca1839 -
Daniel Schürmann authored
Totals from affected shaders: (VEGA) SGPRS: 284392 -> 284400 (0.00 %) VGPRS: 261080 -> 261076 (-0.00 %) Spilled SGPRs: 105 -> 105 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 24698596 -> 24277788 (-1.70 %) bytes LDS: 196 -> 196 (0.00 %) blocks Max Waves: 10101 -> 10105 (0.04 %) Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!4830>
56ec814b -
Daniel Schürmann authored
Totals from affected shaders: (VEGA) SGPRS: 545712 -> 545712 (0.00 %) VGPRS: 413092 -> 413116 (0.01 %) Spilled SGPRs: 10616 -> 10616 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 37031684 -> 36984248 (-0.13 %) bytes LDS: 427 -> 427 (0.00 %) blocks Max Waves: 54350 -> 54340 (-0.02 %) Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!4830>
9d22c5ed -
Daniel Schürmann authored
Totals from affected shaders: (VEGA) SGPRS: 13920 -> 13920 (0.00 %) VGPRS: 10252 -> 10252 (0.00 %) Spilled SGPRs: 62 -> 62 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 587648 -> 587224 (-0.07 %) bytes LDS: 5 -> 5 (0.00 %) blocks Max Waves: 1489 -> 1489 (0.00 %) Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!4830>
70d3efeb -
Daniel Schürmann authored
Totals from 581 (0.43% of 134368) affected shaders (Polaris): CodeSize: 1389560 -> 1386488 (-0.22%) Instrs: 264488 -> 263984 (-0.19%) Cycles: 1057952 -> 1055936 (-0.19%) VMEM: 296016 -> 291613 (-1.49%) Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!4830>
baee5a98 -
Daniel Schürmann authored
Totals from 761 (0.57% of 134368) affected shaders (Polaris): SGPRs: 29496 -> 29488 (-0.03%) SpillSGPRs: 41 -> 43 (+4.88%) CodeSize: 1922036 -> 1882408 (-2.06%); split: -2.08%, +0.02% Instrs: 366051 -> 360362 (-1.55%); split: -1.57%, +0.02% Cycles: 7692516 -> 7661216 (-0.41%); split: -0.41%, +0.01% VMEM: 365175 -> 365172 (-0.00%) VClause: 15324 -> 15322 (-0.01%) SClause: 9825 -> 9824 (-0.01%); split: -0.02%, +0.01% Copies: 41216 -> 41294 (+0.19%); split: -0.01%, +0.20% Branches: 7020 -> 7033 (+0.19%) PreSGPRs: 22103 -> 22106 (+0.01%) PreVGPRs: 26518 -> 26515 (-0.01%) Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!4830>
27244662 -
Daniel Schürmann authored
Totals from 14266 (10.62% of 134368) affected shaders (Polaris): SGPRs: 761756 -> 762732 (+0.13%); split: -0.00%, +0.13% VGPRs: 430392 -> 430924 (+0.12%); split: -0.05%, +0.17% SpillSGPRs: 4652 -> 4628 (-0.52%); split: -0.60%, +0.09% CodeSize: 30133000 -> 29949780 (-0.61%); split: -0.66%, +0.05% MaxWaves: 102122 -> 102111 (-0.01%); split: +0.00%, -0.01% Instrs: 5845085 -> 5841668 (-0.06%); split: -0.08%, +0.03% Cycles: 69033140 -> 68889188 (-0.21%); split: -0.22%, +0.01% VMEM: 8479021 -> 8474978 (-0.05%); split: +0.03%, -0.08% SMEM: 831437 -> 830464 (-0.12%); split: +0.06%, -0.18% VClause: 105411 -> 105410 (-0.00%); split: -0.01%, +0.01% SClause: 327727 -> 327780 (+0.02%); split: -0.00%, +0.02% Copies: 372704 -> 373306 (+0.16%); split: -0.16%, +0.32% Branches: 112260 -> 112269 (+0.01%); split: -0.00%, +0.01% PreSGPRs: 433308 -> 433631 (+0.07%); split: -0.01%, +0.09% PreVGPRs: 397888 -> 397905 (+0.00%); split: -0.01%, +0.01% Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!4830>
5f79e4e6 -
Emma Anholt authored
fd.o has retuned the x86 runners on packet for -j8. Rather than having to tweak our CI every time fd.o decides to rebalance job concurrency, respect what the runner admin has chosen for their builds (this will also be convenient for people with large local runners). Reviewed-by:
Michel Dänzer <michel@daenzer.net> Part-of: <!5669>
fd24a959 -
Faith Ekstrand authored
Acked-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by:
Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <mesa/mesa!5983>
4ab3a219 -
Emma Anholt authored
Part-of: <!5815>
ed3338f5 -
Emma Anholt authored
This started with making note of some ldp/stp instructions from the blob and how we differ from them. In the process of fixing it, I accidentally modified behavior of other opcodes, and the other instructions listed will keep us from doing that. I also dropped an old stl test that looks like I took from after a shader 'end' instruction. Part-of: <!5815>
62dcf754 -
Emma Anholt authored
We didn't need the extra branch and temp, we can move it inside of the dst handling by just duplicating the print of the dst reg. Part-of: <!5815>
d6d8dc13 -
Emma Anholt authored
I had a stp testcase that was getting its offset wrong, and by twiddling bits and feeding it to qc disasm, I found that the comment was sort of right: some the cat6a bits implicated in the old comment do get used, as the high bits of the cat6c offset. Reallocating those bits also fixes how we were getting r960.y for r0.y. Part-of: <!5815>
af92348b -
Yevhenii Kolesnikov authored
According to the "Errors" list of the OpenGL 4.6 spec, section 8.6 "Alternate Texture Image Specification Commands": An INVALID_OPERATION error is generated by *TextureSubImage* if the effective target of texture does not match the command, as shown in table 8.15. Signed-off-by:
Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5934>
101400d4 -
Christian Gmeiner authored
Closes: #2655 Signed-off-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <!5661>
096adbe3 -
Samuel Pitoiset authored
All new dEQP-VK.robustness.image_robustness.* pass. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!5979>
3688da21 -
Emma Anholt authored
It triggers the disk cache for me, and asserts abount not getting the build id right. Fixes: f97acb4b ("freedreno/ir3: disk-cache support") Part-of: <!5989>
d973e50f -
Faith Ekstrand authored
We already support a superset of VK_EXT_image_robustness via VK_EXT_robustness2. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <!5985>
36e6ac65 -
Bas Nieuwenhuizen authored
Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5972>
794ba3ef -
Bas Nieuwenhuizen authored
Otherwise most counters return 0. Should be much more user friendly than having to totally disable clock-gating on the kernel cmdline. Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5972>
7b7917a4
Showing
- .gitlab-ci.yml 14 additions, 19 deletions.gitlab-ci.yml
- .gitlab-ci/bare-metal/fastboot.sh 16 additions, 1 deletion.gitlab-ci/bare-metal/fastboot.sh
- .gitlab-ci/bare-metal/init.sh 12 additions, 0 deletions.gitlab-ci/bare-metal/init.sh
- .gitlab-ci/bare-metal/nginx-default-site 20 additions, 0 deletions.gitlab-ci/bare-metal/nginx-default-site
- .gitlab-ci/container/arm_test-base.sh 5 additions, 0 deletions.gitlab-ci/container/arm_test-base.sh
- .gitlab-ci/container/container_pre_build.sh 3 additions, 8 deletions.gitlab-ci/container/container_pre_build.sh
- .gitlab-ci/create-rootfs.sh 1 addition, 0 deletions.gitlab-ci/create-rootfs.sh
- .gitlab-ci/deqp-freedreno-a630-fails.txt 0 additions, 1 deletion.gitlab-ci/deqp-freedreno-a630-fails.txt
- .gitlab-ci/deqp-radv-navi10-aco-fails.txt 0 additions, 2 deletions.gitlab-ci/deqp-radv-navi10-aco-fails.txt
- .gitlab-ci/deqp-radv-navi14-aco-fails.txt 0 additions, 2 deletions.gitlab-ci/deqp-radv-navi14-aco-fails.txt
- .gitlab-ci/deqp-radv-pitcairn-aco-fails.txt 0 additions, 2 deletions.gitlab-ci/deqp-radv-pitcairn-aco-fails.txt
- .gitlab-ci/deqp-radv-raven-aco-fails.txt 0 additions, 2 deletions.gitlab-ci/deqp-radv-raven-aco-fails.txt
- .gitlab-ci/deqp-runner.sh 4 additions, 0 deletions.gitlab-ci/deqp-runner.sh
- .gitlab-ci/piglit/glslparser.txt 2 additions, 9 deletions.gitlab-ci/piglit/glslparser.txt
- .gitlab-ci/piglit/quick_gl.txt 6 additions, 4 deletions.gitlab-ci/piglit/quick_gl.txt
- .gitlab-ci/piglit/quick_shader.txt 2 additions, 25 deletions.gitlab-ci/piglit/quick_shader.txt
- .gitlab-ci/piglit/run.sh 1 addition, 1 deletion.gitlab-ci/piglit/run.sh
- docs/ci/bare-metal.rst 9 additions, 5 deletionsdocs/ci/bare-metal.rst
- docs/features.txt 2 additions, 2 deletionsdocs/features.txt
- docs/relnotes/new_features.txt 2 additions, 0 deletionsdocs/relnotes/new_features.txt
.gitlab-ci/bare-metal/nginx-default-site
0 → 100644