- Apr 22, 2022
-
-
Dylan Baker authored
-
Dylan Baker authored
-
Dylan Baker authored
-
Closes: mesa/mesa#6246 Signed-off-by: Bozhenko Alexey <oleksii.bozhenko@globallogic.com> Fixes: 64cb143b ("spirv: Fix handling of OpBranchConditional with same THEN and ELSE") Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <mesa/mesa!15929> (cherry picked from commit 25acf1d8)
-
src/gallium/auxiliary/tgsi/tgsi_scan.c:287: scan_src_operand: Assertion `info->sampler_targets[index] == target' failed. assert was being triggered by GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit using the stencil fallback with zink. Fixes: f05dfdde ("u_blitter: fix stencil blit fallback for crocus.") Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!16069> (cherry picked from commit 4b7ba386)
-
When setting the dst framebuffer width height, it might be silly to constrain this beyond the dst resource, but at least constrain it correctly to take account of x/y offsets. This fixes some uses of this as a fallback for zink with GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_stencil_blit Fixes: b4c07a8a ("gallium/util: allow scaling blits for stencil-fallback") Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!16069> (cherry picked from commit dbc264f5)
-
Cc: mesa-stable Ref: https://patchwork.freedesktop.org/series/102701/ Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!16054> (cherry picked from commit d257494e)
-
Without this, it is impossible to export gem handles with write access. This was fixed the same way for i965 (mesa/mesa!10850) and iris (mesa/mesa!10851 ). Cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com>`> Part-of: <mesa/mesa!16057> (cherry picked from commit 5c4906dc)
-
if there is an indirect count, always use it Fixes: 3eb99323 ("aux/draw: add a util function for reading back indirect draw params") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!15963> (cherry picked from commit ec124916)
-
Fixes: 3eb99323 ("aux/draw: add a util function for reading back indirect draw params") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!15963> (cherry picked from commit 07437fa3)
-
this was incorrectly calculating too small of a map region if the stride was less than the size of the struct Fixes: 3eb99323 ("aux/draw: add a util function for reading back indirect draw params") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!15963> (cherry picked from commit efca37d4)
-
this is only possible when tc determines the buffer is not in use and decides to return a pointer immediately, so just give back a staging buffer cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!15979> (cherry picked from commit d7256043)
-
Dylan Baker authored
-
Fixes: 9f3d5e99 ("compiler: Use util/bitset.h for system_values_read") Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!16063> (cherry picked from commit af718674)
-
New "if" blocks were inserted. Fixes: 303378e1 ("intel/rt: Add lowering for combined intersection/any-hit shaders") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <mesa/mesa!15924> (cherry picked from commit 4fddef33)
-
lower_ubo_load_instr may insert "if" blocks. Fixes: 61749b5a ("anv: Add a pass for lowering A64 UBO access") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <mesa/mesa!15924> (cherry picked from commit 5bd3ba5b)
-
There is no reason not to be able to get it. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 34a0ce58 ("anv: add a new execution mode for secondary command buffers") Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <mesa/mesa!15968> (cherry picked from commit 184084e2)
-
VkObjectType and VkDebugReportObjectTypeEXT has the same enum-values. Why the Vulkan WG thought this was a good idea, beats me. But it's what we have to live with now. Anyway, instead of having a statement that implicitly casts two different values from the former to the latter, let's fully relsove the type as the former, and cast the value when using it instead. Fixes: 41318a58 ("vulkan: Use vk_object_base::type for debug_report") Acked-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!15547> (cherry picked from commit b27a2ba4)
-
cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!15978> (cherry picked from commit cd9424d9)
-
the pipe cap is used for gating wideline support, so this will always be 1.0 when not supported furthermore, the previous code wasn't accurately checking line width for tess shaders, breaking tests cc: mesa-stable fixes (nv): KHR-GL46.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!15960> (cherry picked from commit d8b66fcb)
-
if a rendertarget-specified image can't be a rendertarget or a blit dst then it can't be used for the designated functionality and must be rejected cc: mesa-stable fixes hangs on various nv driver versions: dEQP-GLES2.functional.texture.mipmap.2d.generate.rgba5551_fastest Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!15960> (cherry picked from commit 37ac8647)
-
If we change the sate without flushing the bitmap cache, the cache might be rendered with the new scissor, which excludes some parts that should've been rendered with the old state, and vice versa. Cc: mesa-stable Closes: mesa/mesa#6233 Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!15881> (cherry picked from commit dd7278aa)
-
This is used to determine the geometry shader info on GFX9, and it looks like it was broken for topologies that use adjacency. This is also used to remove PSIZ from shaders that don't need it. Found by inspection. fossils-db (Polaris10): Totals from 140 (0.10% of 135960) affected shaders: SGPRs: 10448 -> 9696 (-7.20%) VGPRs: 4376 -> 4264 (-2.56%) CodeSize: 164316 -> 161028 (-2.00%) Instrs: 26449 -> 25767 (-2.58%) Latency: 184448 -> 180468 (-2.16%) InvThroughput: 80772 -> 79092 (-2.08%) VClause: 337 -> 328 (-2.67%); split: -2.97%, +0.30% SClause: 859 -> 813 (-5.36%); split: -5.70%, +0.35% Copies: 1027 -> 790 (-23.08%) PreSGPRs: 2751 -> 2331 (-15.27%) PreVGPRs: 3887 -> 3836 (-1.31%) Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!15948> (cherry picked from commit ed7d8315)
-
We're missing a programming restriction. Hopefully fixing dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.* on Gfx9atoms Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Closes: mesa/mesa#6216 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>.> Tested-by: Mark Janes <markjanes@swizzler.org> Part-of: <mesa/mesa!15596> (cherry picked from commit b07c215c)
-
When we put NIR in the compiler stack for r300, indirect addressing broke for gallium nine. DX's array indirects round the float value, so the DX shader gets mapped to a TGSI "ARR ADDR[0] src.x" instruction. Translating that to NIR maps to r0[f2i32(fround(src.x))]. While we might hope that in translation back using nir-to-tgsi after optimization we would recognize the construct and emit ARR again, that's going to be error prone (think "what if src.x is in a NIR register?") so we need a fallback plan. r300 will be able to handle this lowering, so get it in place first to fix the regression. Fixes: #6297 Fixes: 7d2ea9b0 ("r300: Request NIR shaders from mesa/st and use NIR-to-TGSI.") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!15870> (cherry picked from commit 6947016b)
-
The line stride uses the number of bytes in the entire block, so both the width and height need to be reduced for compressed textures so that the surface stride is calculated correctly. Fixes: 051d62cf ("panfrost: Add a pan_image_layout_init() helper") Closes: mesa/mesa#6286 Part-of: <mesa/mesa!15989> (cherry picked from commit f2670002)
-
Otherwise constant-folding will fold it to 0/1 instead of 0/~0. Fixes: 330e2815 ("nir: add 32-bit bool of fisfinite") Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!15984> (cherry picked from commit 5c9e4d40)
-
the shaders will never see these, so set the expected value for 2D cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!15895> (cherry picked from commit 2058ae7b)
-
queries still need the sampler_dim changed Fixes: 682e14d3 ("nir: lower_tex: Don't normalize coordinates for TXF with RECT") Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!15895> (cherry picked from commit 5b0634d7)
-
Fixes: 4d219b0e ("iris: implement scratch space!") Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!15897> (cherry picked from commit 6ca32898)
-
this is illegal affects: KHR-GL46.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-packed-matC cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!15894> (cherry picked from commit fcd6b2a4)
-
this may or may not be 1 cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!15894> (cherry picked from commit ff4dcb76)
-
When stream output is active, we need to let the cache tracker know about any SO buffers, which we access via IRIS_DOMAIN_OTHER_WRITE. In particular, we may have written to those buffers via another mechanism, such as BLORP buffer copies. In that case, previous writes happened via IRIS_DOMAIN_RENDER_WRITE, in which case we'd need to flush both the render cache and the tile cache to make that data globally- observable before we begin writing via streamout, which is incoherent with the earlier mechanism. Fixes misrendering in Ryujinx. Closes: mesa/mesa#6085 Fixes: d8cb7621 ("iris: Fix MOCS for buffer copies") Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <mesa/mesa!15275> (cherry picked from commit 9c8874b9)
-
e551040c, which added a new mechanism for 64-bit imul which is more efficient on BDW and later Intel hardware also introduced a bug where we weren't properly walking both X and Y. No idea how testing didn't find this. Fixes: e551040c ("nir/glsl: Add another way of doing lower_imul64 for gen8+" Closes: mesa/mesa#6306 Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <mesa/mesa!15829> (cherry picked from commit d0ace287)
-
Dylan Baker authored
-
Fixes: a6031cd9 ("anv: fix push constant lowering with bindless shaders") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!15850> (cherry picked from commit f844ce66)
-
This tripped up some pointsize/prim id interactions with zink. Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Cc: mesa-stable Part-of: <mesa/mesa!15872> (cherry picked from commit 60c61d7b)
-
The pvtmem was split off to a separate read/write BO. Fixes: 931ad19a ("turnip: make cmdstream bo's read-only to GPU") Part-of: <mesa/mesa!15038> (cherry picked from commit e0fbdd3e)
-
The intel_perf_query path used for performance queries on GL was passing a bogus "end" pointer to intel_perf_query_result_accumulate(), causing it to accumulate garbage values. This was causing the values of many performance counters to be corrupted. The "end" pointer was incorrect because the current code was assuming that different OA reports were located TOTAL_QUERY_DATA_SIZE bytes apart, which is a hard-coded preprocessor define. However recent (Gfx12+) hardware generations use a variable query size determined by the query layout. Use the size derived from it instead, and remove the stale define. Fixes: 3c513250 ("intel/perf: switch query code to use query layout") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!15783> (cherry picked from commit e858da39)
-
I missed these in the previous fix to mimic GLSL-to-TGSI address reg behavior, which r600 relies on. Fixes: 4bb9c0a2 ("nir_to_tgsi: Use the same address reg mappings as GLSL-to-TGSI did.") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!15824> (cherry picked from commit e15154a7) Conflicts: src/gallium/auxiliary/nir/nir_to_tgsi.c
-