iris: Update cache tracker to handle L3 coherency and tile cache flushes

This picks up @currojerez's remaining patches from !5018, replacing the rest of my dubious history-based flushes with his actual cache tracker mechanism, which is a lot more robust.

It then extends the cache tracker to understand L3 coherency. Modern Intel GPUs have updated most hardware units to use a shared L3 cache. The old render target and depth cache flushes no longer make memory globally observable, but instead simply flush out L1/L2 caches, leaving the data in L3, where it can be picked up by other units (say the sampler or vertex fetcher). A new "Tile Cache Flush" option flushes color/depth out of L3 so that writes are globally-observable. We can avoid flushing that in many cases, but need to be sure to do so when accessing the same memory via a non-L3 client.

When we first added tile cache support, we had simply tied it to render and depth flushing, preserving the old behavior, but negating any performance gain from retaining the shared L3 and avoiding the flushes. More recently, we started dropping the tile cache flush...but have run into many problems, where we missed flushes, and have been applying dubious-quality band-aids ever since.

With this series, the cache tracker actually understands when to insert Tile Cache flushes, which should make this much more reliable. It also moves to using HDC flushes and avoiding data cache invalidation and L3 flushes there, which should improve performance a bit.

As evidence that this really helps, the series fixes rendering in Ryujinx (#6085 (closed)) due to missed tile cache flushes when transitioning from blorp buffer copies to stream output writes.

My most sincere thanks to @currojerez for not only designing the new cache tracker, but patiently helping me work through the many bugs in earlier versions of this series over the course of many hours.