- May 10, 2023
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Eric Engestrom authored
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Resolves ambient occlusion rendering in Replicant Resolves grass and ocean animations in Automata, and maybe more. Both of these games have shaders that expect trig values to work across large ranges with good precision. Closes #7656 Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Part-of: <mesa/mesa!22894> (cherry picked from commit 7accfbff)
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a semaphore is a semaphore, as they say Fixes: 7399b224 ("zink: move semaphore caching to zink_reset_batch_state()") Part-of: <mesa/mesa!22935> (cherry picked from commit e9f18f64)
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Fixes: 89aa3635 ("zink: block oom flushes during unordered blits") Part-of: <mesa/mesa!22931> (cherry picked from commit c6fd5880)
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buffer handle ids are offset by ZINK_MAX_BINDLESS_HANDLES, but the actual index is zero-based Fixes: 99ba529f ("zink: implement descriptor buffer handling of bindless texture") Part-of: <mesa/mesa!22931> (cherry picked from commit 2df7ee52)
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the bindless flag here isn't set, so this check did nothing Fixes: e3b746e3 ("zink: use GPL to handle (simple) separate shader objects") Part-of: <mesa/mesa!22931> (cherry picked from commit 8ef098a6)
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this otherwise doesn't bind a bindless set and hangs Fixes: e3b746e3 ("zink: use GPL to handle (simple) separate shader objects") Part-of: <mesa/mesa!22931> (cherry picked from commit 2991a7c1)
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The 'struct drm_amdgpu_cs_chunk_fence' is processed as 'struct drm_amdgpu_cs_chunk_data' which is a union. This change ensures the proper alignment for this structure to be processed as 'struct drm_amdgpu_cs_chunk_data'. The presence of __u64 as one member of 'struct drm_amdgpu_cs_chunk_data' makes the whole structure expected to be 64-bit aligned. This is a minor issue detected by the gcc sanitizer (ubsan), for instance at the libdrm library: ../amdgpu/amdgpu_cs.c:937:26: runtime error: member access within misaligned address 0x63100001484c for type 'struct drm_amdgpu_cs_chunk_data', which requires 8 byte alignment 0x63100001484c: note: pointer points here 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ^ Fixes: ae7e4d76 ("amd: rename ring_type --> amd_ip_type and match the kernel enum values") Signed-off-by: Patrick Lerda <patrick9876@free.fr> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22920> (cherry picked from commit acdd6a2a)
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Eric Engestrom authored
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- May 09, 2023
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CC: mesa-stable Part-of: <mesa/mesa!22924> (cherry picked from commit 57afa7c0)
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if a sampler is never used (no derefs) then its binding will never be applied here, leaving it with binding=0. this will clobber the real binding=0 sampler in driver backends, leading to errors, so try to iterate using the same criteria as above and apply bindings in the same way fixes #8974 cc: mesa-stable Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Part-of: <mesa/mesa!22902> (cherry picked from commit ccbfcf39)
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Fixes: db0e9d3c ("ac/nir/ngg: support line culling") Closes: mesa/mesa#8950 Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <mesa/mesa!22867> (cherry picked from commit 1ba2460e)
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the inner conditional here didn't include uncached readback, meaning that many (most?) buffers allocated with uncached memory (i.e., BAR) were being read back directly instead of using staging resources to be faster at some point this inner conditional should be reevaluated to determine whether it still does anything, but this is not that time fixes, among other things, loading in DOOM2016 on some GPUs Fixes: 52f27cda ("zink: allow direct memory mapping for any COHERENT+CACHED buffer") Part-of: <mesa/mesa!22907> (cherry picked from commit 24350064)
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in the case where a cmdbuf was submitted with write access and the subsequent batch promotes an op to unordered, it's important for associated barriers to happen-before those ops to guarantee synchronization the fixes tag is wrong on this, but it's all in the same release Fixes: bf0af0f8 ("zink: move all barrier-related functions to c++") Part-of: <mesa/mesa!22907> (cherry picked from commit 6452849b)
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another improvement for debugging Fixes: bf0af0f8 ("zink: move all barrier-related functions to c++") Part-of: <mesa/mesa!22907> (cherry picked from commit 9b4b0911)
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this is usable in gfx and compute, so don't desync Fixes: 3674839d ("zink: batch mem barrier hooks") Part-of: <mesa/mesa!22907> (cherry picked from commit 4b724528)
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this otherwise breaks ssbo binding cc: mesa-stable Part-of: <mesa/mesa!22907> (cherry picked from commit 5149b2a9)
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this makes the bug more obvious cc: mesa-stable Part-of: <mesa/mesa!22907> (cherry picked from commit 2f0749f8)
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I added these for completeness, but zink will never use them cc: mesa-stable Part-of: <mesa/mesa!22907> (cherry picked from commit ecb4e6af)
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Fixes: 13c6ad00 ("zink: use a single descriptor buffer for all non-bindless types") Part-of: <mesa/mesa!22907> (cherry picked from commit 98c411a2)
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this was never needed and never did anything: zink only uses COHERENT memory, which is always available on queue submission, so it was all just pointless code cc: mesa-stable Part-of: <mesa/mesa!22907> (cherry picked from commit 8e75378a)
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cc: mesa-stable Part-of: <mesa/mesa!22760> (cherry picked from commit 95df5f2e)
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this is a weird case but whatever cc: mesa-stable Part-of: <mesa/mesa!22760> (cherry picked from commit e205a483)
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fixes #8993 cc: 23.1 <mesa-stable> Part-of: <mesa/mesa!22876> (cherry picked from commit b4ea6add)
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these are either already mutable (for srgb) or invalid usage fixes #8970 cc: mesa-stable Part-of: <mesa/mesa!22876> (cherry picked from commit d2c63624)
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Otherwise accesses to non-0 views of input attachments may be considered out-of-bounds and return 0. This should've been removed when enabling multiview for GMEM, not sure how it was missed. Fixes: def56b53 ("tu: Support GMEM with layered rendering and multiview") Part-of: <mesa/mesa!20304> (cherry picked from commit f6902bf4)
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Closes: #8222 Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!21313> (cherry picked from commit 87d31cad)
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We go to initialize the disk cache before we've compiled any shaders so agx_compiler_debug is 0 at this point. Don't try to read it, instead go through sa safe getter that will do the right thing. Fixes: 5e9538c1 ("agx: isolate compiler debug flags") Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!22891> (cherry picked from commit e9b471d1)
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The typo is in the !__GLIBC__ case and was observed while building on Alpine. Fixes: 0a132b06 ("asahi: Add a helper macro for debug/error messages") Reported-by: mps Tested-by: mps Signed-off-by: Janne Grunau <j@jannau.net> Part-of: <mesa/mesa!22891> (cherry picked from commit 222d6b45)
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Fixes: 01dfd65a ("nir: port fp16 casting code from dxil") Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <mesa/mesa!22804> (cherry picked from commit 5503a085)
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Makes piglits related to texturequerylod and samplercubearray pass. Fixes: 79ca456b ("r600/sfn: rewrite NIR backend") Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <mesa/mesa!22883> (cherry picked from commit 1ae09f3e)
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Closes: mesa/mesa#8971 Fixes: 79ca456b ("r600/sfn: rewrite NIR backend") Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <mesa/mesa!22883> (cherry picked from commit 05a3eba0)
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Eric Engestrom authored
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- May 05, 2023
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S8_UINT is not a requirement for Vulkan 1.0. Revert "pvr: Add initial support for VK_FORMAT_S8_UINT". This reverts commit 220356e0. Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com> Reviewed-by: Frank Binns <frank.binns@imgtec.com> Part-of: <mesa/mesa!22822> (cherry picked from commit 0aafa22a)
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It no longer 100% crashes, but instead sometimes fails. Fixes: 91b06ea8 ("Uprev Piglit to 2391a83d1639a7ab7bbea02853b922878687b0e5") Part-of: <mesa/mesa!22863> (cherry picked from commit a8af5040)
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reason: in some cases, bs buffer size could cause assertion, and some bitstreams of certain resolutions could not be decoded. solution: to align the bs buffer to 128. fixes: 4f1646d7 Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <mesa/mesa!22844> (cherry picked from commit 499f332a)
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These asserts were checking isl_format_layout against itself, change to compare surface format layout against view format layout. Fixes: 628bfaf1 ("intel/isl: Add some sanity checks for compressed surfaces") Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!22790> (cherry picked from commit c35d4304)
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With the following test : dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.no_out_of_bounds_load There is a : shader_start: ... <- no control flow g0 = some_alu g1 = fbl g2 = broadcast g3, g1 g4 = get_buffer_size g2 ... <- no control flow halt <- on some lanes g5 = send <surface>, g4 eliminate_find_live_channel will remove the fbl/broadcast because it assumes lane0 is active at get_buffer_size : shader_start: ... <- no control flow g0 = some_alu g4 = get_buffer_size g0 ... <- no control flow halt <- on some lanes g5 = send <surface>, g4 But then the instruction scheduler will move the get_buffer_size after the halt : shader_start: ... <- no control flow halt <- on some lanes g0 = some_alu g4 = get_buffer_size g0 g5 = send <surface>, g4 get_buffer_size pulls the surface index from lane0 in g0 which could have been turned off by the halt and we end up accessing an invalid surface handle. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <mesa/mesa!20765> (cherry picked from commit 9471ffa7)
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Cc: mesa-stable Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <mesa/mesa!22690> (cherry picked from commit 38447b3f)
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The pv mode emulation code was not taking into account the location_frac of variables, they where beeing stored in a 1D array leading to collisions. Fixes: 5a408334 ("zink: add provoking vertex mode lowering") Part-of: <mesa/mesa!22856> (cherry picked from commit 96cd034e)
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