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  • coypoop/xf86-video-intel
  • adamjrichter/xf86-video-intel
  • banzr/xf86-video-intel
  • E5ten/xf86-video-intel
  • ross/xf86-video-intel
  • thomas.preston/xf86-video-intel
  • hanno/xf86-video-intel
  • Ma/xf86-video-intel
  • airlied/xf86-video-intel
  • develomentional/xf86-video-intel
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Commits on Source (53)
Showing with 454 additions and 164 deletions
......@@ -24,7 +24,7 @@
AC_PREREQ([2.60])
AC_INIT([xf86-video-intel],
[2.99.917],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[https://gitlab.freedesktop.org/xorg/driver/xf86-video-intel/issues/new],
[xf86-video-intel])
AC_CONFIG_SRCDIR([Makefile.am])
AC_CONFIG_HEADERS([config.h])
......
......@@ -108,8 +108,10 @@
INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
#define INTEL_PINEVIEW_IDS(info) \
INTEL_VGA_DEVICE(0xa001, info), \
#define INTEL_PINEVIEW_G_IDS(info) \
INTEL_VGA_DEVICE(0xa001, info)
#define INTEL_PINEVIEW_M_IDS(info) \
INTEL_VGA_DEVICE(0xa011, info)
#define INTEL_IRONLAKE_D_IDS(info) \
......@@ -166,7 +168,18 @@
#define INTEL_IVB_Q_IDS(info) \
INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
#define INTEL_HSW_ULT_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */
#define INTEL_HSW_ULX_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
#define INTEL_HSW_GT1_IDS(info) \
INTEL_HSW_ULT_GT1_IDS(info), \
INTEL_HSW_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
......@@ -175,20 +188,26 @@
INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
#define INTEL_HSW_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */
#define INTEL_HSW_ULX_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
#define INTEL_HSW_GT2_IDS(info) \
INTEL_HSW_ULT_GT2_IDS(info), \
INTEL_HSW_ULX_GT2_IDS(info), \
INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
......@@ -197,9 +216,6 @@
INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
......@@ -207,11 +223,17 @@
INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
#define INTEL_HSW_ULT_GT3_IDS(info) \
INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
#define INTEL_HSW_GT3_IDS(info) \
INTEL_HSW_ULT_GT3_IDS(info), \
INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
......@@ -220,16 +242,11 @@
INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
#define INTEL_HSW_IDS(info) \
......@@ -245,35 +262,59 @@
INTEL_VGA_DEVICE(0x0157, info), \
INTEL_VGA_DEVICE(0x0155, info)
#define INTEL_BDW_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
#define INTEL_BDW_ULT_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
INTEL_VGA_DEVICE(0x160B, info) /* GT1 Iris */
#define INTEL_BDW_ULX_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */
#define INTEL_BDW_GT1_IDS(info) \
INTEL_BDW_ULT_GT1_IDS(info), \
INTEL_BDW_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
#define INTEL_BDW_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
#define INTEL_BDW_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
INTEL_VGA_DEVICE(0x161B, info) /* GT2 ULT */
#define INTEL_BDW_ULX_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
#define INTEL_BDW_GT2_IDS(info) \
INTEL_BDW_ULT_GT2_IDS(info), \
INTEL_BDW_ULX_GT2_IDS(info), \
INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
#define INTEL_BDW_ULT_GT3_IDS(info) \
INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
INTEL_VGA_DEVICE(0x162B, info) /* Iris */ \
#define INTEL_BDW_ULX_GT3_IDS(info) \
INTEL_VGA_DEVICE(0x162E, info) /* ULX */
#define INTEL_BDW_GT3_IDS(info) \
INTEL_BDW_ULT_GT3_IDS(info), \
INTEL_BDW_ULX_GT3_IDS(info), \
INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
INTEL_VGA_DEVICE(0x162E, info), /* ULX */\
INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
#define INTEL_BDW_ULT_RSVD_IDS(info) \
INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
INTEL_VGA_DEVICE(0x163B, info) /* Iris */
#define INTEL_BDW_ULX_RSVD_IDS(info) \
INTEL_VGA_DEVICE(0x163E, info) /* ULX */
#define INTEL_BDW_RSVD_IDS(info) \
INTEL_BDW_ULT_RSVD_IDS(info), \
INTEL_BDW_ULX_RSVD_IDS(info), \
INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \
INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
......@@ -289,25 +330,40 @@
INTEL_VGA_DEVICE(0x22b2, info), \
INTEL_VGA_DEVICE(0x22b3, info)
#define INTEL_SKL_ULT_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
#define INTEL_SKL_ULX_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
#define INTEL_SKL_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
INTEL_SKL_ULT_GT1_IDS(info), \
INTEL_SKL_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
#define INTEL_SKL_GT2_IDS(info) \
#define INTEL_SKL_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
INTEL_VGA_DEVICE(0x1921, info) /* ULT GT2F */
#define INTEL_SKL_ULX_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */
#define INTEL_SKL_GT2_IDS(info) \
INTEL_SKL_ULT_GT2_IDS(info), \
INTEL_SKL_ULX_GT2_IDS(info), \
INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
#define INTEL_SKL_ULT_GT3_IDS(info) \
INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
#define INTEL_SKL_GT3_IDS(info) \
INTEL_SKL_ULT_GT3_IDS(info), \
INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
......@@ -336,45 +392,91 @@
INTEL_VGA_DEVICE(0x3184, info), \
INTEL_VGA_DEVICE(0x3185, info)
#define INTEL_KBL_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
#define INTEL_KBL_ULT_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
INTEL_VGA_DEVICE(0x5913, info) /* ULT GT1.5 */
#define INTEL_KBL_ULX_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
INTEL_VGA_DEVICE(0x5915, info) /* ULX GT1.5 */
#define INTEL_KBL_GT1_IDS(info) \
INTEL_KBL_ULT_GT1_IDS(info), \
INTEL_KBL_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
#define INTEL_KBL_GT2_IDS(info) \
#define INTEL_KBL_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
INTEL_VGA_DEVICE(0x5921, info) /* ULT GT2F */
#define INTEL_KBL_ULX_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x591E, info) /* ULX GT2 */
#define INTEL_KBL_GT2_IDS(info) \
INTEL_KBL_ULT_GT2_IDS(info), \
INTEL_KBL_ULX_GT2_IDS(info), \
INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
#define INTEL_KBL_ULT_GT3_IDS(info) \
INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */
#define INTEL_KBL_GT3_IDS(info) \
INTEL_KBL_ULT_GT3_IDS(info), \
INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
#define INTEL_KBL_GT4_IDS(info) \
INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
/* AML/KBL Y GT2 */
#define INTEL_AML_GT2_IDS(info) \
#define INTEL_AML_KBL_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \
INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
/* AML/CFL Y GT2 */
#define INTEL_AML_CFL_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x87CA, info)
/* CML GT1 */
#define INTEL_CML_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x9BA5, info), \
INTEL_VGA_DEVICE(0x9BA8, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
INTEL_VGA_DEVICE(0x9BA2, info)
#define INTEL_CML_U_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x9B21, info), \
INTEL_VGA_DEVICE(0x9BAA, info), \
INTEL_VGA_DEVICE(0x9BAC, info)
/* CML GT2 */
#define INTEL_CML_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BC4, info), \
INTEL_VGA_DEVICE(0x9BC2, info), \
INTEL_VGA_DEVICE(0x9BC6, info), \
INTEL_VGA_DEVICE(0x9BE6, info), \
INTEL_VGA_DEVICE(0x9BF6, info)
#define INTEL_CML_U_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x9B41, info), \
INTEL_VGA_DEVICE(0x9BCA, info), \
INTEL_VGA_DEVICE(0x9BCC, info)
#define INTEL_KBL_IDS(info) \
INTEL_KBL_GT1_IDS(info), \
INTEL_KBL_GT2_IDS(info), \
INTEL_KBL_GT3_IDS(info), \
INTEL_KBL_GT4_IDS(info), \
INTEL_AML_GT2_IDS(info)
INTEL_AML_KBL_GT2_IDS(info)
/* CFL S */
#define INTEL_CFL_S_GT1_IDS(info) \
......@@ -390,6 +492,9 @@
INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
/* CFL H */
#define INTEL_CFL_H_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x3E9C, info)
#define INTEL_CFL_H_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
......@@ -407,30 +512,43 @@
/* WHL/CFL U GT1 */
#define INTEL_WHL_U_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x3EA1, info)
INTEL_VGA_DEVICE(0x3EA1, info), \
INTEL_VGA_DEVICE(0x3EA4, info)
/* WHL/CFL U GT2 */
#define INTEL_WHL_U_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x3EA0, info)
INTEL_VGA_DEVICE(0x3EA0, info), \
INTEL_VGA_DEVICE(0x3EA3, info)
/* WHL/CFL U GT3 */
#define INTEL_WHL_U_GT3_IDS(info) \
INTEL_VGA_DEVICE(0x3EA2, info), \
INTEL_VGA_DEVICE(0x3EA3, info), \
INTEL_VGA_DEVICE(0x3EA4, info)
INTEL_VGA_DEVICE(0x3EA2, info)
#define INTEL_CFL_IDS(info) \
INTEL_CFL_S_GT1_IDS(info), \
INTEL_CFL_S_GT2_IDS(info), \
INTEL_CFL_H_GT1_IDS(info), \
INTEL_CFL_H_GT2_IDS(info), \
INTEL_CFL_U_GT2_IDS(info), \
INTEL_CFL_U_GT3_IDS(info), \
INTEL_WHL_U_GT1_IDS(info), \
INTEL_WHL_U_GT2_IDS(info), \
INTEL_WHL_U_GT3_IDS(info)
INTEL_WHL_U_GT3_IDS(info), \
INTEL_AML_CFL_GT2_IDS(info), \
INTEL_CML_GT1_IDS(info), \
INTEL_CML_GT2_IDS(info), \
INTEL_CML_U_GT1_IDS(info), \
INTEL_CML_U_GT2_IDS(info)
/* CNL */
#define INTEL_CNL_PORT_F_IDS(info) \
INTEL_VGA_DEVICE(0x5A54, info), \
INTEL_VGA_DEVICE(0x5A5C, info), \
INTEL_VGA_DEVICE(0x5A44, info), \
INTEL_VGA_DEVICE(0x5A4C, info)
#define INTEL_CNL_IDS(info) \
INTEL_CNL_PORT_F_IDS(info), \
INTEL_VGA_DEVICE(0x5A51, info), \
INTEL_VGA_DEVICE(0x5A59, info), \
INTEL_VGA_DEVICE(0x5A41, info), \
......@@ -440,22 +558,47 @@
INTEL_VGA_DEVICE(0x5A42, info), \
INTEL_VGA_DEVICE(0x5A4A, info), \
INTEL_VGA_DEVICE(0x5A50, info), \
INTEL_VGA_DEVICE(0x5A40, info), \
INTEL_VGA_DEVICE(0x5A54, info), \
INTEL_VGA_DEVICE(0x5A5C, info), \
INTEL_VGA_DEVICE(0x5A44, info), \
INTEL_VGA_DEVICE(0x5A4C, info)
INTEL_VGA_DEVICE(0x5A40, info)
/* ICL */
#define INTEL_ICL_11_IDS(info) \
#define INTEL_ICL_PORT_F_IDS(info) \
INTEL_VGA_DEVICE(0x8A50, info), \
INTEL_VGA_DEVICE(0x8A51, info), \
INTEL_VGA_DEVICE(0x8A5C, info), \
INTEL_VGA_DEVICE(0x8A5D, info), \
INTEL_VGA_DEVICE(0x8A59, info), \
INTEL_VGA_DEVICE(0x8A58, info), \
INTEL_VGA_DEVICE(0x8A52, info), \
INTEL_VGA_DEVICE(0x8A5A, info), \
INTEL_VGA_DEVICE(0x8A5B, info), \
INTEL_VGA_DEVICE(0x8A57, info), \
INTEL_VGA_DEVICE(0x8A56, info), \
INTEL_VGA_DEVICE(0x8A71, info), \
INTEL_VGA_DEVICE(0x8A70, info)
INTEL_VGA_DEVICE(0x8A70, info), \
INTEL_VGA_DEVICE(0x8A53, info), \
INTEL_VGA_DEVICE(0x8A54, info)
#define INTEL_ICL_11_IDS(info) \
INTEL_ICL_PORT_F_IDS(info), \
INTEL_VGA_DEVICE(0x8A51, info), \
INTEL_VGA_DEVICE(0x8A5D, info)
/* EHL/JSL */
#define INTEL_EHL_IDS(info) \
INTEL_VGA_DEVICE(0x4500, info), \
INTEL_VGA_DEVICE(0x4571, info), \
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info), \
INTEL_VGA_DEVICE(0x4E71, info), \
INTEL_VGA_DEVICE(0x4E61, info), \
INTEL_VGA_DEVICE(0x4E51, info)
/* TGL */
#define INTEL_TGL_12_IDS(info) \
INTEL_VGA_DEVICE(0x9A49, info), \
INTEL_VGA_DEVICE(0x9A40, info), \
INTEL_VGA_DEVICE(0x9A59, info), \
INTEL_VGA_DEVICE(0x9A60, info), \
INTEL_VGA_DEVICE(0x9A68, info), \
INTEL_VGA_DEVICE(0x9A70, info), \
INTEL_VGA_DEVICE(0x9A78, info)
#endif /* _I915_PCIIDS_H */
......@@ -301,9 +301,9 @@ static int open_cloexec(const char *path)
#ifdef __linux__
static int __intel_open_device__major_minor(int _major, int _minor)
{
char path[256];
DIR *dir;
struct dirent *de;
char path[9+sizeof(de->d_name)];
int base, fd = -1;
base = sprintf(path, "/dev/dri/");
......
......@@ -142,6 +142,22 @@ static const struct intel_device_info intel_coffeelake_info = {
.gen = 0114,
};
static const struct intel_device_info intel_cannonlake_info = {
.gen = 0120,
};
static const struct intel_device_info intel_icelake_info = {
.gen = 0130,
};
static const struct intel_device_info intel_elkhartlake_info = {
.gen = 0131,
};
static const struct intel_device_info intel_tigerlake_info = {
.gen = 0140,
};
static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_I810, "i810"},
{PCI_CHIP_I810_DC100, "i810-dc100"},
......@@ -307,7 +323,7 @@ static const SymTabRec intel_chipsets[] = {
{0x5916, "HD Graphics 620"},
{0x591E, "HD Graphics 615"},
/*Coffeelake*/
/* Coffeelake */
{0x3E90, "HD Graphics"},
{0x3E93, "HD Graphics"},
{0x3E99, "HD Graphics"},
......@@ -315,8 +331,10 @@ static const SymTabRec intel_chipsets[] = {
{0x3E92, "HD Graphics"},
{0x3E96, "HD Graphics"},
{0x3E9A, "HD Graphics"},
{0x3E9C, "HD Graphics"},
{0x3E9B, "HD Graphics"},
{0x3E94, "HD Graphics"},
{0x3E98, "HD Graphics"},
{0x3EA1, "HD Graphics"},
{0x3EA4, "HD Graphics"},
{0x3EA0, "HD Graphics"},
......@@ -327,6 +345,75 @@ static const SymTabRec intel_chipsets[] = {
{0x3EA6, "HD Graphics"},
{0x3EA7, "HD Graphics"},
{0x3EA8, "HD Graphics"},
{0x87CA, "HD Graphics"},
{0x9BA5, "HD Graphics"},
{0x9BA8, "HD Graphics"},
{0x9BA4, "HD Graphics"},
{0x9BA2, "HD Graphics"},
{0x9BC5, "HD Graphics"},
{0x9BC8, "HD Graphics"},
{0x9BC4, "HD Graphics"},
{0x9BC2, "HD Graphics"},
{0x9BC6, "HD Graphics"},
{0x9BE6, "HD Graphics"},
{0x9BF6, "HD Graphics"},
{0x9B21, "HD Graphics"},
{0x9BAA, "HD Graphics"},
{0x9BAC, "HD Graphics"},
{0x9B41, "HD Graphics"},
{0x9BCA, "HD Graphics"},
{0x9BCC, "HD Graphics"},
/* CannonLake */
{0x5A54, "HD Graphics"},
{0x5A5C, "HD Graphics"},
{0x5A44, "HD Graphics"},
{0x5A4C, "HD Graphics"},
{0x5A51, "HD Graphics"},
{0x5A59, "HD Graphics"},
{0x5A41, "HD Graphics"},
{0x5A49, "HD Graphics"},
{0x5A52, "HD Graphics"},
{0x5A5A, "HD Graphics"},
{0x5A42, "HD Graphics"},
{0x5A4A, "HD Graphics"},
{0x5A50, "HD Graphics"},
{0x5A40, "HD Graphics"},
/* IceLake */
{0x8A50, "HD Graphics"},
{0x8A5C, "HD Graphics"},
{0x8A59, "HD Graphics"},
{0x8A58, "HD Graphics"},
{0x8A52, "HD Graphics"},
{0x8A5A, "HD Graphics"},
{0x8A5B, "HD Graphics"},
{0x8A57, "HD Graphics"},
{0x8A56, "HD Graphics"},
{0x8A71, "HD Graphics"},
{0x8A70, "HD Graphics"},
{0x8A53, "HD Graphics"},
{0x8A54, "HD Graphics"},
{0x8A51, "HD Graphics"},
{0x8A5D, "HD Graphics"},
/* ElkhartLake */
{0x4500, "HD Graphics"},
{0x4571, "HD Graphics"},
{0x4551, "HD Graphics"},
{0x4541, "HD Graphics"},
{0x4E71, "HD Graphics"},
{0x4E61, "HD Graphics"},
{0x4E51, "HD Graphics"},
/* TigerLake */
{0x9A49, "HD Graphics"},
{0x9A40, "HD Graphics"},
{0x9A59, "HD Graphics"},
{0x9A60, "HD Graphics"},
{0x9A68, "HD Graphics"},
{0x9A70, "HD Graphics"},
{0x9A78, "HD Graphics"},
/* When adding new identifiers, also update:
* 1. intel_identify()
......@@ -357,7 +444,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_I945GM_IDS(&intel_i945_info),
INTEL_G33_IDS(&intel_g33_info),
INTEL_PINEVIEW_IDS(&intel_g33_info),
INTEL_PINEVIEW_G_IDS(&intel_g33_info),
INTEL_PINEVIEW_M_IDS(&intel_g33_info),
INTEL_I965G_IDS(&intel_i965_info),
INTEL_I965GM_IDS(&intel_i965_info),
......@@ -376,19 +464,27 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_HSW_IDS(&intel_haswell_info),
INTEL_VLV_IDS(&intel_valleyview_info),
INTEL_BDW_IDS(&intel_broadwell_info),
INTEL_CHV_IDS(&intel_cherryview_info),
INTEL_SKL_IDS(&intel_skylake_info),
INTEL_BXT_IDS(&intel_broxton_info),
INTEL_KBL_IDS(&intel_kabylake_info),
INTEL_GLK_IDS(&intel_geminilake_info),
INTEL_CFL_IDS(&intel_coffeelake_info),
INTEL_CNL_IDS(&intel_cannonlake_info),
INTEL_ICL_11_IDS(&intel_icelake_info),
INTEL_EHL_IDS(&intel_elkhartlake_info),
INTEL_TGL_12_IDS(&intel_tigerlake_info),
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
#endif
{ 0, 0, 0 },
{},
};
void
......@@ -692,6 +788,7 @@ static Bool intel_pci_probe(DriverPtr driver,
case PCI_CHIP_I815:
if (!hosted())
break;
/* fall through */
default:
return FALSE;
}
......
......@@ -322,6 +322,6 @@ extern void I810InitMC(ScreenPtr pScreen);
extern const OptionInfoRec *I810AvailableOptions(int chipid, int busid);
extern const int I810CopyROP[16];
const int I810PatternROP[16];
extern const int I810PatternROP[16];
#endif /* _I810_H_ */
......@@ -1246,8 +1246,8 @@ static __inline__ void renderFieldinField(uint **datay,uint **datau,
*dy++ = (1<<30) | (3<<28) | dw1;
*dy++ = xy;
*dy++ = (16<<16) | 16;
*dy++ = *(uint *)fmv;
*dy++ = *(uint *)bmv;
*dy++ = fmv[1] << 16 | fmv[0];
*dy++ = bmv[1] << 16 | bmv[0];
PACK_CORR_DATA(dy,block_ptr,ysize);
block_ptr = (short *)((unsigned long)block_ptr + ysize);
/* End Y Blocks */
......@@ -1263,8 +1263,8 @@ static __inline__ void renderFieldinField(uint **datay,uint **datau,
*du++ = (2<<30) | (1<<28) | dw1;
*du++ = xy;
*du++ = (8<<16) | 8;
*du++ = *(uint *)fmv;
*du++ = *(uint *)bmv;
*du++ = fmv[1] << 16 | fmv[0];
*du++ = bmv[1] << 16 | bmv[0];
PACK_CORR_DATA(du,block_ptr,usize);
block_ptr = (short *)((unsigned long)block_ptr + usize);
......@@ -1273,8 +1273,8 @@ static __inline__ void renderFieldinField(uint **datay,uint **datau,
*dv++ = (3<<30) | (1<<28) | dw1;
*dv++ = xy;
*dv++ = (8<<16) | 8;
*dv++ = *(uint *)fmv;
*dv++ = *(uint *)bmv;
*dv++ = fmv[1] << 16 | fmv[0];
*dv++ = bmv[1] << 16 | bmv[0];
PACK_CORR_DATA(dv,block_ptr,vsize);
block_ptr = (short *)((unsigned long)block_ptr + vsize);
......@@ -1394,8 +1394,8 @@ static __inline__ void render16x8inField(uint **datay,uint **datau,
*dy++ = (1<<30) | (2<<28) | dw1[0];
*dy++ = xy;
*dy++ = (8<<16) | 16;
*dy++ = *(uint *)fmv;
*dy++ = *(uint *)bmv;
*dy++ = fmv[1] << 16 | fmv[0];
*dy++ = bmv[1] << 16 | bmv[0];
PACK_CORR_DATA(dy,block_ptr,y1size);
block_ptr = (short *)((unsigned long)block_ptr + y1size);
......@@ -1404,8 +1404,8 @@ static __inline__ void render16x8inField(uint **datay,uint **datau,
*dy++ = (1<<30) | (2<<28) | dw1[1];
*dy++ = (xy + 8);
*dy++ = (8<<16) | 16;
*dy++ = *(uint *)&fmv[2];
*dy++ = *(uint *)&bmv[2];
*dy++ = fmv[3] << 16 | fmv[2];
*dy++ = bmv[3] << 16 | bmv[2];
PACK_CORR_DATA(dy,block_ptr,y2size);
block_ptr = (short *)((unsigned long)block_ptr + y2size);
/* End Y Blocks */
......@@ -1427,8 +1427,8 @@ static __inline__ void render16x8inField(uint **datay,uint **datau,
*du++ = (2<<30) | (1<<28) | dw1[0];
*du++ = xy;
*du++ = (4<<16) | 8;
*du++ = *(uint *)fmv;
*du++ = *(uint *)bmv;
*du++ = fmv[1] << 16 | fmv[0];
*du++ = bmv[1] << 16 | bmv[0];
PACK_CORR_DATA(du,block_ptr,usize);
block_ptr = (short *)((unsigned long)block_ptr + usize);
......@@ -1437,8 +1437,8 @@ static __inline__ void render16x8inField(uint **datay,uint **datau,
*du++ = (2<<30) | (1<<28) | dw1[1];
*du++ = (xy + 4);
*du++ = (4<<16) | 8;
*du++ = *(uint *)&fmv[2];
*du++ = *(uint *)&bmv[2];
*du++ = fmv[3] << 16 | fmv[2];
*du++ = bmv[3] << 16 | bmv[2];
PACK_CORR_DATA(du,block_ptr,usize);
block_ptr = (short *)((unsigned long)block_ptr + usize);
/* End U Blocks */
......@@ -1448,8 +1448,8 @@ static __inline__ void render16x8inField(uint **datay,uint **datau,
*dv++ = (3<<30) | (1<<28) | dw1[0];
*dv++ = xy;
*dv++ = (4<<16) | 8;
*dv++ = *(uint *)fmv;
*dv++ = *(uint *)bmv;
*dv++ = fmv[1] << 16 | fmv[0];
*dv++ = bmv[1] << 16 | bmv[0];
PACK_CORR_DATA(dv,block_ptr,vsize);
block_ptr = (short *)((unsigned long)block_ptr + vsize);
......@@ -1458,8 +1458,8 @@ static __inline__ void render16x8inField(uint **datay,uint **datau,
*dv++ = (3<<30) | (1<<28) | dw1[1];
*dv++ = (xy + 4);
*dv++ = (4<<16) | 8;
*dv++ = *(uint *)&fmv[2];
*dv++ = *(uint *)&bmv[2];
*dv++ = fmv[3] << 16 | fmv[2];
*dv++ = bmv[3] << 16 | bmv[2];
PACK_CORR_DATA(dv,block_ptr,vsize);
block_ptr = (short *)((unsigned long)block_ptr + vsize);
/* End V Blocks */
......@@ -1513,8 +1513,8 @@ static __inline__ void renderDualPrimeinField(uint **datay,uint **datau,
*dy++ = (1<<30) | (3<<28) | dw1;
*dy++ = xy;
*dy++ = (16<<16) | 16;
*dy++ = *(uint *)fmv;
*dy++ = *(uint *)bmv;
*dy++ = fmv[1] << 16 | fmv[0];
*dy++ = bmv[1] << 16 | bmv[0];
PACK_CORR_DATA(dy,block_ptr,ysize);
block_ptr = (short *)((unsigned long)block_ptr + ysize);
/* End Y Blocks */
......@@ -1530,8 +1530,8 @@ static __inline__ void renderDualPrimeinField(uint **datay,uint **datau,
*du++ = (2<<30) | (1<<28) | dw1;
*du++ = xy;
*du++ = (8<<16) | 8;
*du++ = *(uint *)fmv;
*du++ = *(uint *)bmv;
*du++ = fmv[1] << 16 | fmv[0];
*du++ = bmv[1] << 16 | bmv[0];
PACK_CORR_DATA(du,block_ptr,usize);
block_ptr = (short *)((unsigned long)block_ptr + usize);
......@@ -1540,8 +1540,8 @@ static __inline__ void renderDualPrimeinField(uint **datay,uint **datau,
*dv++ = (3<<30) | (1<<28) | dw1;
*dv++ = xy;
*dv++ = (8<<16) | 8;
*dv++ = *(uint *)fmv;
*dv++ = *(uint *)bmv;
*dv++ = fmv[1] << 16 | fmv[0];
*dv++ = bmv[1] << 16 | bmv[0];
PACK_CORR_DATA(dv,block_ptr,vsize);
block_ptr = (short *)((unsigned long)block_ptr + vsize);
......
......@@ -150,7 +150,6 @@ shared_module('intel_drv',
'-DMAJOR_IN_SYSMACROS',
'-Wno-unused-parameter',
'-Wno-sign-compare',
'-Wno-missing-field-initializers',
],
name_prefix : '',
install_dir : join_paths(moduledir, 'drivers'),
......
......@@ -1404,6 +1404,7 @@ memcpy_xor(const void *src, void *dst, int bpp,
width /= 2;
or |= or << 8;
}
/* fall through */
case 2:
if (width & 1) {
do {
......@@ -1421,6 +1422,7 @@ memcpy_xor(const void *src, void *dst, int bpp,
width /= 2;
or |= or << 16;
}
/* fall through */
case 4:
w = width;
if (w * 4 == dst_stride && dst_stride == src_stride) {
......
......@@ -32,7 +32,7 @@
#define likely(expr) (__builtin_expect (!!(expr), 1))
#define unlikely(expr) (__builtin_expect (!!(expr), 0))
#define noinline __attribute__((noinline))
#define force_inline inline __attribute__((always_inline))
#define force_inline inline /* __attribute__((always_inline)) */
#define fastcall __attribute__((regparm(3)))
#define must_check __attribute__((warn_unused_result))
#define constant __attribute__((const))
......@@ -50,7 +50,7 @@
#define must_check
#define constant
#define pure
#define tighly_packed
#define tightly_packed
#define flatten
#define nonnull
#define page_aligned
......
......@@ -185,11 +185,13 @@ typedef int FbStride;
FbStorePart(dst,sizeof (FbBits) - 3,CARD8,xor); \
FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \
break; \
case sizeof (FbBits) - 3: \
FbStorePart(dst,sizeof (FbBits) - 3,CARD8,xor); \
FbStorePart(dst,sizeof (FbBits) - 2,CARD16,xor); \
break; \
case (sizeof (FbBits) - 2) | (1 << (FB_SHIFT - 3)): \
FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \
break; \
case sizeof (FbBits) - 3: \
FbStorePart(dst,sizeof (FbBits) - 3,CARD8,xor); \
case sizeof (FbBits) - 2: \
FbStorePart(dst,sizeof (FbBits) - 2,CARD16,xor); \
break; \
......
......@@ -313,8 +313,10 @@ image_from_pict_internal(PicturePtr pict, Bool has_clip, int *xoff, int *yoff,
{
pixman_image_t *image = NULL;
if (!pict)
if (!pict) {
*xoff = *yoff = 0;
return NULL;
}
if (pict->pDrawable) {
image = create_bits_picture(pict, has_clip, xoff, yoff);
......@@ -336,6 +338,8 @@ image_from_pict_internal(PicturePtr pict, Bool has_clip, int *xoff, int *yoff,
image = create_conical_gradient_image(gradient);
}
*xoff = *yoff = 0;
} else {
*xoff = *yoff = 0;
}
if (image)
......
......@@ -39,12 +39,13 @@ fbFillSpans(DrawablePtr drawable, GCPtr gc,
while (n--) {
BoxRec box;
*(DDXPointPtr)&box = *pt++;
memcpy(&box, pt, sizeof(box));
box.x2 = box.x1 + *width++;
box.y2 = box.y1 + 1;
/* XXX fSorted */
fbDrawableRun(drawable, gc, &box, fbFillSpan, NULL);
pt++;
}
}
......@@ -91,7 +92,8 @@ fbSetSpans(DrawablePtr drawable, GCPtr gc,
while (n--) {
BoxRec box;
*(DDXPointPtr)&box = data.pt = *pt;
memcpy(&box, pt, sizeof(box));
data.pt = *pt;
box.x2 = box.x1 + *width;
box.y2 = box.y1 + 1;
......
......@@ -116,10 +116,17 @@ gen2_buf_tiling(uint32_t tiling)
{
uint32_t v = 0;
switch (tiling) {
default: assert(0);
case I915_TILING_Y: v |= BUF_3D_TILE_WALK_Y;
case I915_TILING_X: v |= BUF_3D_TILED_SURFACE;
case I915_TILING_NONE: break;
default:
assert(0);
/* fall through */
case I915_TILING_Y:
v |= BUF_3D_TILE_WALK_Y;
/* fall through */
case I915_TILING_X:
v |= BUF_3D_TILED_SURFACE;
/* fall through */
case I915_TILING_NONE:
break;
}
return v;
}
......@@ -131,6 +138,7 @@ gen2_get_dst_format(uint32_t format)
switch (format) {
default:
assert(0);
/* fall through */
case PICT_a8r8g8b8:
case PICT_x8r8g8b8:
return COLR_BUF_ARGB8888 | BIAS;
......@@ -219,10 +227,13 @@ gen2_sampler_tiling_bits(uint32_t tiling)
switch (tiling) {
default:
assert(0);
/* fall through */
case I915_TILING_Y:
bits |= TM0S1_TILE_WALK;
/* fall through */
case I915_TILING_X:
bits |= TM0S1_TILED_SURFACE;
/* fall through */
case I915_TILING_NONE:
break;
}
......@@ -277,6 +288,7 @@ gen2_emit_texture(struct sna *sna,
switch (channel->repeat) {
default:
assert(0);
/* fall through */
case RepeatNone:
wrap_mode_u = TEXCOORDMODE_CLAMP_BORDER;
break;
......@@ -298,6 +310,7 @@ gen2_emit_texture(struct sna *sna,
switch (channel->filter) {
default:
assert(0);
/* fall through */
case PictFilterNearest:
filter = (FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT |
FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |
......
......@@ -131,9 +131,14 @@ static inline uint32_t gen3_buf_tiling(uint32_t tiling)
{
uint32_t v = 0;
switch (tiling) {
case I915_TILING_Y: v |= BUF_3D_TILE_WALK_Y;
case I915_TILING_X: v |= BUF_3D_TILED_SURFACE;
case I915_TILING_NONE: break;
case I915_TILING_Y:
v |= BUF_3D_TILE_WALK_Y;
/* fall through */
case I915_TILING_X:
v |= BUF_3D_TILED_SURFACE;
/* fall through */
case I915_TILING_NONE:
break;
}
return v;
}
......@@ -400,6 +405,7 @@ static uint32_t gen3_filter(uint32_t filter)
switch (filter) {
default:
assert(0);
/* fall through */
case PictFilterNearest:
return (FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
FILTER_NEAREST << SS2_MIN_FILTER_SHIFT |
......@@ -1884,9 +1890,14 @@ static uint32_t gen3_ms_tiling(uint32_t tiling)
{
uint32_t v = 0;
switch (tiling) {
case I915_TILING_Y: v |= MS3_TILE_WALK;
case I915_TILING_X: v |= MS3_TILED_SURFACE;
case I915_TILING_NONE: break;
case I915_TILING_Y:
v |= MS3_TILE_WALK;
/* fall through */
case I915_TILING_X:
v |= MS3_TILED_SURFACE;
/* fall through */
case I915_TILING_NONE:
break;
}
return v;
}
......@@ -4981,6 +4992,7 @@ gen3_render_composite_spans(struct sna *sna,
switch (tmp->base.src.u.gen3.type) {
case SHADER_NONE:
assert(0);
/* fall through */
case SHADER_ZERO:
if (no_offset) {
tmp->prim_emit = gen3_emit_composite_spans_primitive_zero_no_offset;
......
......@@ -883,6 +883,9 @@ gen4_emit_invariant(struct sna *sna)
else
OUT_BATCH(GEN4_PIPELINE_SELECT | PIPELINE_SELECT_3D);
OUT_BATCH(GEN4_CONSTANT_BUFFER);
OUT_BATCH(0);
gen4_emit_state_base_address(sna);
sna->render_state.gen4.needs_invariant = false;
......@@ -2016,7 +2019,7 @@ gen4_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
if (mask == NULL &&
sna_blt_composite__convert(sna,
......@@ -2068,7 +2071,7 @@ gen4_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->mask, 0))
goto cleanup_src;
/* fall through to fixup */
/* fall through */
case 1:
gen4_composite_channel_convert(&tmp->mask);
break;
......@@ -2325,7 +2328,7 @@ gen4_render_composite_spans(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->base.src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
gen4_composite_channel_convert(&tmp->base.src);
break;
......
......@@ -1972,7 +1972,7 @@ gen5_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
if (mask == NULL &&
sna_blt_composite__convert(sna,
......@@ -2023,7 +2023,7 @@ gen5_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->mask, 0))
goto cleanup_src;
/* fall through to fixup */
/* fall through */
case 1:
gen5_composite_channel_convert(&tmp->mask);
break;
......@@ -2268,7 +2268,7 @@ gen5_render_composite_spans(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->base.src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
gen5_composite_channel_convert(&tmp->base.src);
break;
......
......@@ -43,15 +43,15 @@ inline static bool can_switch_to_blt(struct sna *sna,
struct kgem_bo *bo,
unsigned flags)
{
if (sna->kgem.ring != KGEM_RENDER)
if (bo && bo->tiling == I915_TILING_Y)
return false;
if (PREFER_RENDER < 0 && sna->kgem.ring != KGEM_RENDER)
return true;
if (bo && RQ_IS_BLT(bo->rq))
return true;
if (bo && bo->tiling == I915_TILING_Y)
return false;
if (bo && !kgem_bo_can_blt(&sna->kgem, bo))
return false;
......@@ -87,41 +87,45 @@ static int prefer_blt_bo(struct sna *sna,
if (PREFER_RENDER)
return PREFER_RENDER < 0;
if (dst->rq)
return RQ_IS_BLT(dst->rq);
if (sna->flags & SNA_POWERSAVE)
return true;
if (dst->tiling == I915_TILING_Y)
return false;
if (src) {
if (sna->render_state.gt > 1)
return false;
if (src->rq)
return RQ_IS_BLT(src->rq);
if (src->tiling == I915_TILING_Y)
return false;
if (src->rq)
return RQ_IS_BLT(src->rq);
} else {
if (sna->render_state.gt > 2)
return false;
}
if (dst->rq)
return RQ_IS_BLT(dst->rq);
if (sna->flags & SNA_POWERSAVE)
return true;
if (sna->render_state.gt < 2)
return true;
return dst->tiling == I915_TILING_NONE || is_uncached(sna, dst);
}
inline static bool force_blt_ring(struct sna *sna, struct kgem_bo *bo)
inline static bool
force_blt_ring(struct sna *sna, struct kgem_bo *dst, struct kgem_bo *src)
{
if (sna->kgem.mode == KGEM_RENDER)
if (sna->kgem.ring != KGEM_BLT)
return false;
if (NO_RING_SWITCH(sna))
return sna->kgem.ring == KGEM_BLT;
return sna->kgem.mode == KGEM_BLT;
if (bo->tiling == I915_TILING_Y)
if (kgem_bo_is_render(dst) || (src && kgem_bo_is_render(src)))
return false;
if (sna->flags & SNA_POWERSAVE)
......@@ -139,10 +143,10 @@ prefer_blt_ring(struct sna *sna, struct kgem_bo *bo, unsigned flags)
if (PREFER_RENDER)
return PREFER_RENDER < 0;
assert(!force_blt_ring(sna, bo));
assert(!force_blt_ring(sna, bo, NULL));
assert(!kgem_bo_is_render(bo) || NO_RING_SWITCH(sna));
if (kgem_bo_is_blt(bo))
if (!sna->kgem.has_semaphores && kgem_bo_is_blt(bo))
return true;
return can_switch_to_blt(sna, bo, flags);
......@@ -179,7 +183,7 @@ prefer_blt_composite(struct sna *sna, struct sna_composite_op *tmp)
untiled_tlb_miss(tmp->src.bo))
return true;
if (force_blt_ring(sna, tmp->dst.bo))
if (force_blt_ring(sna, tmp->dst.bo, tmp->src.bo))
return true;
if (prefer_render_ring(sna, tmp->dst.bo))
......@@ -200,7 +204,7 @@ prefer_blt_fill(struct sna *sna, struct kgem_bo *bo, unsigned flags)
if (untiled_tlb_miss(bo))
return true;
if (force_blt_ring(sna, bo))
if (force_blt_ring(sna, bo, NULL))
return true;
if ((flags & (FILL_POINTS | FILL_SPANS)) == 0) {
......
......@@ -2346,7 +2346,7 @@ gen6_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
/* Did we just switch rings to prepare the source? */
if (mask == NULL &&
......@@ -2399,7 +2399,7 @@ gen6_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->mask, 0))
goto cleanup_src;
/* fall through to fixup */
/* fall through */
case 1:
gen6_composite_channel_convert(&tmp->mask);
break;
......@@ -2653,7 +2653,7 @@ gen6_render_composite_spans(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->base.src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
gen6_composite_channel_convert(&tmp->base.src);
break;
......@@ -2761,7 +2761,7 @@ static inline bool prefer_blt_copy(struct sna *sna,
untiled_tlb_miss(dst_bo))
return true;
if (force_blt_ring(sna, dst_bo))
if (force_blt_ring(sna, dst_bo, src_bo))
return true;
if (kgem_bo_is_render(dst_bo) ||
......
......@@ -2576,7 +2576,7 @@ gen7_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
/* Did we just switch rings to prepare the source? */
if (mask == NULL &&
......@@ -2629,7 +2629,7 @@ gen7_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->mask, 0))
goto cleanup_src;
/* fall through to fixup */
/* fall through */
case 1:
gen7_composite_channel_convert(&tmp->mask);
break;
......@@ -2863,7 +2863,7 @@ gen7_render_composite_spans(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->base.src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
gen7_composite_channel_convert(&tmp->base.src);
break;
......@@ -2969,7 +2969,7 @@ prefer_blt_copy(struct sna *sna,
if (flags & COPY_DRI && !sna->kgem.has_semaphores)
return false;
if (force_blt_ring(sna, dst_bo))
if (force_blt_ring(sna, dst_bo, src_bo))
return true;
if ((flags & COPY_SMALL ||
......
......@@ -2084,11 +2084,6 @@ try_blt(struct sna *sna,
{
struct kgem_bo *bo;
if (sna->kgem.mode == KGEM_BLT) {
DBG(("%s: already performing BLT\n", __FUNCTION__));
goto execute;
}
if (too_large(width, height)) {
DBG(("%s: operation too large for 3D pipe (%d, %d)\n",
__FUNCTION__, width, height));
......@@ -2129,7 +2124,7 @@ try_blt(struct sna *sna,
goto execute;
}
if (sna->kgem.ring == KGEM_BLT) {
if (sna->kgem.mode == KGEM_BLT) {
DBG(("%s: already performing BLT\n", __FUNCTION__));
goto execute;
}
......@@ -2410,7 +2405,7 @@ gen8_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
/* Did we just switch rings to prepare the source? */
if (mask == NULL &&
......@@ -2466,7 +2461,7 @@ gen8_render_composite(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->mask, 0))
goto cleanup_src;
/* fall through to fixup */
/* fall through */
case 1:
if (!gen8_composite_channel_convert(&tmp->mask))
goto cleanup_mask;
......@@ -2701,7 +2696,7 @@ gen8_render_composite_spans(struct sna *sna,
case 0:
if (!gen4_channel_init_solid(sna, &tmp->base.src, 0))
goto cleanup_dst;
/* fall through to fixup */
/* fall through */
case 1:
if (!gen8_composite_channel_convert(&tmp->base.src))
goto cleanup_src;
......@@ -2796,40 +2791,53 @@ prefer_blt_copy(struct sna *sna,
struct kgem_bo *dst_bo,
unsigned flags)
{
if (sna->kgem.mode == KGEM_BLT)
return true;
assert((flags & COPY_SYNC) == 0);
if (untiled_tlb_miss(src_bo) ||
untiled_tlb_miss(dst_bo))
untiled_tlb_miss(dst_bo)) {
DBG(("%s: TLB miss -> blt\n", __func__));
return true;
}
if (flags & COPY_DRI && !sna->kgem.has_semaphores)
if (flags & COPY_DRI && !sna->kgem.has_semaphores) {
DBG(("%s: DRI -> render\n", __func__));
return false;
}
if (force_blt_ring(sna, dst_bo))
if (force_blt_ring(sna, dst_bo, src_bo)) {
DBG(("%s: force BLT -> blt\n", __func__));
return true;
}
if ((flags & COPY_SMALL ||
(sna->render_state.gt < 3 && src_bo == dst_bo)) &&
can_switch_to_blt(sna, dst_bo, flags))
can_switch_to_blt(sna, dst_bo, flags)) {
DBG(("%s: small/self copy -> blt\n", __func__));
return true;
}
if (kgem_bo_is_render(dst_bo) ||
kgem_bo_is_render(src_bo))
kgem_bo_is_render(src_bo)) {
DBG(("%s: render bo -> render\n", __func__));
return false;
}
if (flags & COPY_LAST &&
sna->render_state.gt < 3 &&
can_switch_to_blt(sna, dst_bo, flags))
can_switch_to_blt(sna, dst_bo, flags)) {
DBG(("%s: copy last -> blt\n", __func__));
return true;
}
if (prefer_render_ring(sna, dst_bo))
if (prefer_render_ring(sna, dst_bo)) {
DBG(("%s: prefer render -> render\n", __func__));
return false;
}
if (!prefer_blt_ring(sna, dst_bo, flags))
if (!prefer_blt_ring(sna, dst_bo, flags)) {
DBG(("%s: !prefer blt -> render\n", __func__));
return false;
}
return prefer_blt_bo(sna, src_bo, dst_bo);
}
......@@ -3116,6 +3124,7 @@ gen8_render_copy(struct sna *sna, uint8_t alu,
unaligned(src_bo, src->drawable.bitsPerPixel) ||
unaligned(dst_bo, dst->drawable.bitsPerPixel)) {
fallback:
DBG(("%s: blt fallback\n", __func__));
if (!sna_blt_compare_depth(&src->drawable, &dst->drawable))
return false;
......