- Aug 27, 2020
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Thierry Reding authored
Implements fence FDs based on new libdrm API and the accompanying IOCTL. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Michel Dänzer authored
Pre-merge pipelines for MRs appear to run in the target project namespace now, so we have to explicitly rule those out. Part-of: <!6481>
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Samuel Pitoiset authored
To disable value numbering, optimizations and scheduling. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Part-of: <mesa/mesa!6470>
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Bas Nieuwenhuizen authored
- the offsets are inclusive-exclusive so the +1 was wrong - Since the GPU doesn't do the interpolation on depth (as we render per layer), we have to add an offset for the pixel center. CC: mesa-stable Closes: mesa/mesa#3073 Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!6458>
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- Aug 26, 2020
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Marek Olšák authored
It's not needed. Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <!6465>
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Emma Anholt authored
I've been hacking on softpipe in the process of trying to delete a bunch of core Mesa code, and want to make sure I don't regress desktop GL either. The run takes under a minute and a half. Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Part-of: <mesa/mesa!6466>
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Rhys Perry authored
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <!6424>
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Rhys Perry authored
If the offset is large enough, it could affect the width. I'm also not sure if the hardware masks the offset by 0x1f. Found by inspection. No fossil-db changes. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <!6424>
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Rhys Perry authored
ubfe/ibfe is always 32-bit. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <!6424>
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Rhys Perry authored
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <!6212>
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Rhys Perry authored
Future tests will do this. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <!6212>
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Rhys Perry authored
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <!6212>
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Rhys Perry authored
When the branch offset can't be encoded, we have to use s_setpc_b64. Fixes hang in RPCS3 vertex ubershader. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Closes: #3231 Cc: 20.2 <mesa-stable> Part-of: <!6212>
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Rhys Perry authored
We'll need two sgprs for the possibility of a long jump. fossil-db (Navi): Totals from 10197 (7.50% of 135946) affected shaders: SGPRs: 946268 -> 946468 (+0.02%) VGPRs: 705884 -> 707956 (+0.29%); split: -0.00%, +0.30% SpillSGPRs: 31485 -> 36212 (+15.01%); split: -0.04%, +15.05% CodeSize: 88296484 -> 88384604 (+0.10%); split: -0.01%, +0.11% MaxWaves: 81379 -> 81171 (-0.26%) Instrs: 17219111 -> 17231682 (+0.07%); split: -0.03%, +0.10% Cycles: 1594875900 -> 1596450136 (+0.10%); split: -0.05%, +0.15% VMEM: 1687263 -> 1689080 (+0.11%); split: +0.14%, -0.03% SMEM: 657726 -> 660262 (+0.39%); split: +0.61%, -0.22% VClause: 294806 -> 294638 (-0.06%); split: -0.08%, +0.02% SClause: 556702 -> 556210 (-0.09%); split: -0.12%, +0.03% Copies: 1466323 -> 1469349 (+0.21%); split: -0.57%, +0.78% Branches: 619793 -> 618556 (-0.20%); split: -0.28%, +0.08% PreSGPRs: 806364 -> 811477 (+0.63%); split: -0.14%, +0.77% PreVGPRs: 655845 -> 657174 (+0.20%) Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Cc: 20.2 <mesa-stable> Part-of: <mesa/mesa!6212>
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Rhys Perry authored
fossil-db (Navi): Totals from 3149 (2.32% of 135946) affected shaders: VGPRs: 280928 -> 280932 (+0.00%) SpillSGPRs: 51133 -> 30042 (-41.25%) CodeSize: 43063076 -> 41377252 (-3.91%); split: -3.92%, +0.00% Instrs: 8278435 -> 8037133 (-2.91%); split: -2.92%, +0.00% Cycles: 709575456 -> 683366172 (-3.69%); split: -3.69%, +0.00% VMEM: 542887 -> 542937 (+0.01%); split: +0.05%, -0.04% SMEM: 210255 -> 206368 (-1.85%); split: +0.12%, -1.97% SClause: 258847 -> 258019 (-0.32%); split: -0.52%, +0.20% Copies: 731836 -> 684784 (-6.43%); split: -6.44%, +0.01% Branches: 305422 -> 292844 (-4.12%); split: -4.12%, +0.00% PreSGPRs: 333103 -> 332701 (-0.12%) PreVGPRs: 280086 -> 280089 (+0.00%) Helps mostly Detroit: Become Human and the single spilling Doom Eternal shader. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Cc: 20.2 <mesa-stable> Part-of: <mesa/mesa!6212>
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Rhys Perry authored
fossil-db (Navi): Totals from 222 (0.16% of 135946) affected shaders: SpillSGPRs: 9121 -> 9117 (-0.04%) SpillVGPRs: 2820 -> 1821 (-35.43%) CodeSize: 5134264 -> 5053336 (-1.58%); split: -1.63%, +0.05% Instrs: 953435 -> 938761 (-1.54%); split: -1.59%, +0.05% Cycles: 100567688 -> 97252432 (-3.30%); split: -3.34%, +0.04% VMEM: 40752 -> 39219 (-3.76%); split: +0.04%, -3.80% SMEM: 15416 -> 15509 (+0.60%); split: +0.64%, -0.03% VClause: 20120 -> 19091 (-5.11%) SClause: 23540 -> 23544 (+0.02%); split: -0.11%, +0.12% Copies: 125912 -> 122017 (-3.09%); split: -3.36%, +0.26% Branches: 31131 -> 30009 (-3.60%) Mostly affects parallel-rdp ubershaders. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Cc: 20.2 <mesa-stable> Part-of: <mesa/mesa!6212>
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Rhys Perry authored
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Cc: 20.2 <mesa-stable> Part-of: <!6212>
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Rhys Perry authored
This would move the old exec mask back into exec. This also fixes the live_out_exec. Issue found in dEQP-VK.graphicsfuzz.cosh-return-inf-unused Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Cc: 20.2 <mesa-stable> Part-of: <!6212>
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Rhys Perry authored
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Cc: 20.2 <mesa-stable> Part-of: <mesa/mesa!6212>
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Rhys Perry authored
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Cc: 20.2 <mesa-stable> Part-of: <mesa/mesa!6212>
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Samuel Pitoiset authored
Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!6468>
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Marek Vasut authored
The content of rsc->pending_ctx could be changed from multiple contexts and thus from multiple threads. The per-context lock is not sufficient to protect this list. Add per-resource lock to protect this list. Fixes: e5cc66df ("etnaviv: Rework locking") Signed-off-by:
Marek Vasut <marex@denx.de> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <!6454>
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Marek Vasut authored
This function is not used, remove it. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <mesa/mesa!6454>
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Lukas F. Hartmann authored
The VIVS_PE_DEPTH_CONFIG_DISABLE_ZS in PE_DEPTH_CONFIG caused depth write hangs on HALTI5. This is because the 0x11000000 bits in RA have to be toggled on when setting this bit to zero. This combination will disable early-z rejection on GC7000L, which was previously done through a different bit. Tested only on GC7000L so far. Signed-off-by:
Lukas F. Hartmann <lukas@mntre.com> Reviewed-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <!5456>
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Samuel Pitoiset authored
While TRAP_PRESENT is always at the same place, EXCP_EN can be different between shader stages. This sets it properly. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!6452>
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Alejandro Piñeiro authored
PTB assumes that base instance to be 0 at start of tile, but hw would not do that, we need to set it. It is worth to note that the opcode name is somewhat confusing as what it really sets is the base instance. We could rename the opcode, but then the name would be different to the original Broadcom name, so confusing in any case. This fixes several dEQP-GLES3 and dEQP-GLES31 tests that passes individually, but started to fail depending on other tests running before using base instance different to zero. This is the backport of a Vulkan patch that fixed some Vulkan CTS tests that start to fails after some other tests used an instance id. CC: 20.2 20.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <mesa/mesa!6447>
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Alejandro Piñeiro authored
Fixes: 276d22c5 ("v3d: Add some more new packets for V3D 4.x.") CC: 20.2 20.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <!6447>
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Emma Anholt authored
As with a6xx (commits beb02a78, 5785bcc8), the blob doesn't set this flag for a5xx when fragcoords are used but not proper varyings. See for example dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_xyz. The hope was that this would clear up separate_shader fails/flakes like it helped with a6xx's flakes, but that didn't happen. Part-of: <!6464>
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- Aug 25, 2020
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Nanley Chery authored
Return the actual number of planes in these formats (one) instead of the number of planes used for lowering (two). Fixes: d5c85783 ("gallium/dri2: Fix creation of multi-planar modifier images") Acked-by:
Anuj Phogat <anuj.phogat@gmail.com> Part-of: <!6449>
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Emma Anholt authored
We got another flake, this time on dEQP-GLES31.functional.compute.shared_var.atomic.compswap.highp_uint, which blocked !4162 from merging. Mark the rest flaky so we don't have to keep firefighting one test at a time. Part-of: <!6459>
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Faith Ekstrand authored
All three passes have the same bug where, in the mov/vec case they unconditionally return true even if they don't change anything. Throw in a bit size check so they return false properly. Reviewed-by:
Karol Herbst <kherbst@redhat.com> Part-of: <!6435>
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Rob Clark authored
It seems we do have some limits. Similar to older gens, # of tiles per pipe cannot be more than 32. But I could not trigger any hangs with 16 or more tiles per pipe in either X or Y direction, so that limit does not seem to apply. Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!6461>
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Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!6461>
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Rob Clark authored
Sometimes it is useful to force a smaller size while debugging. Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!6461>
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Rob Clark authored
Fixes: f6f8a190 ("freedreno/a6xx: split up gmem/tile alignment requirements") Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!6461>
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Marek Olšák authored
This fixes: KHR-GL45.gl_spirv.spirv_modules_positive_test Fixes: 75ce078a "radeonsi: enable NIR by default and document GL 4.6 support" Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!6460>
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Indrajit Kumar Das authored
Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!6289>
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Mark Menzynski authored
Adds shader disk caching for nvc0 to reduce the need to every time compile shaders. Shaders are saved into disk_shader_cache from nvc0_screen structure. It serializes the input nv50_ir_prog_info to compute the hash key and also to do a byte compare between the original nv50_ir_prog_info and the one saved in the cache. If keys match and also the byte compare returns they are equal, shaders are same, and the compiled nv50_ir_prog_info_out from the cache can be used instead of compiling input info. Seems to be significantly improving loading times, these are the results from running bunch of shaders: cache off real 2m58.574s user 21m34.018s sys 0m8.055s cache on, first run real 3m32.617s user 24m52.701s sys 0m20.400s cache on, second run real 0m23.745s user 2m43.566s sys 0m4.532s Signed-off-by:
Mark Menzynski <mmenzyns@redhat.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!4264>
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Mark Menzynski authored
Adds a function for serializing a nv50_ir_prog_info structure, which is needed for shader caching. v2 (Karol): strip nir when serializing Signed-off-by:
Mark Menzynski <mmenzyns@redhat.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!4264>
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Mark Menzynski authored
Adds a function for printing nv50_ir_prog_info_out structure in JSON-like format, which could be used in debugging. Signed-off-by:
Mark Menzynski <mmenzyns@redhat.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!4264>
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