etnaviv: Fix disabling early-z rejection on GC7000L (HALTI5)
The VIVS_PE_DEPTH_CONFIG_DISABLE_ZS in PE_DEPTH_CONFIG caused depth write hangs on HALTI5. This is because the 0x11000000 bits in RA have to be toggled on when setting this bit to zero. This combination will disable early-z rejection on GC7000L, which was previously done through a different bit. Tested only on GC7000L so far.
Signed-off-by: Lukas F. Hartmann email@example.com
Reviewed-by: Christian Gmeiner firstname.lastname@example.org