Commits on Source (59)
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Timothy Arceri authored
Fixes: e630271e ("mesa: don't ever set NullBufferObj in gl_vertex_array_binding") Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <!5730>
ec8fdf85 -
Timothy Arceri authored
It's warning-clean. Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Michel Dänzer <mdaenzer@redhat.com> Reviewed-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <!5730>
a1b89dbc -
Vinson Lee authored
Fixes: fb2fe802 ("nir: add lowering pass for clip plane enabling") Closes: #3217 Signed-off-by:
Vinson Lee <vlee@freedesktop.org> Reviewed-by:
Timothy Arceri <tarceri@itsqueeze.com> Part-of: <!5741>
395511d1 -
Jonathan Marek authored
ir3 already calculates the stride in the tess param bo, so use that instead of a incorrect calculation. The calculation of per_vertex_output_size / per_patch_output_size is wrong because it counts dwords instead of bytes, and what it counts for per_vertex_output_size is a per-patch size because the glsl type is already an array of # vertex/patch elements. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Part-of: <!5743>
19f3c79c -
Benjamin Cheng authored
The compton compositor is unmaintained, with a new fork named picom taking its place. As with the other compositors (including compton), adaptive sync should not be enabled. Reviewed-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <!5740>
a573c8cd -
Eric Engestrom authored
Let's consistently use the following code format instead of relying on falling through to `default`: if (!req) return GL_INVALID_OPERATION; break; Signed-off-by:
Eric Engestrom <eric@engestrom.ch> Reviewed-by:
Timothy Arceri <tarceri@itsqueeze.com> Part-of: <!5729>
9e2afe4f -
Ilia Mirkin authored
A3xx GPUs support RG8 and RGBA8, but not R8 for rendering. Add RG8 as fallbacks for integer formats, and require a renderable format to be picked for all R8 variants. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5748>
ef11d5fc -
Jonathan Marek authored
Avoids having to duplicate logic to figure out the write mask on D24S8 Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Part-of: <!4600>
37cd3c25 -
Jonathan Marek authored
Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Part-of: <!4600>
7af2a0b9 -
Jonathan Marek authored
Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Part-of: <!4600>
1a83279d -
Dave Airlie authored
I haven't tested all the limits, but these two should be enough for driver writers to realise. I've also submitted a minmax test for piglit to test this. Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5727>
0ca26602 -
Dave Airlie authored
Do we need to make this more dynamic? or have some options for vmware embedded? Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!5724>
df6682d7 -
Dave Airlie authored
Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <!5724>
28ebc8a2 -
Dave Airlie authored
mostly just docs patch, features were all complete already Part-of: <!5724>
2550531d -
Marcin Ślusarz authored
Some Piglit tests (rightfully) fail because of min >= max when exposed to perf counters that do not explicitly define their max value. Failing tests: spec/amd_performance_monitor/api/test_counter_info spec/amd_performance_monitor/vc4/test_counter_info u32/u64 changes are no-ops. Fixes: 4cd1cfb9 ("st/mesa: implement GL_AMD_performance_monitor") Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!5473>
2f4a112e -
Marcin Ślusarz authored
glGetPerfMonitorCounterInfoAMD(..., ..., GL_COUNTER_RANGE_AMD, ...) returned NAN (binary representation of uint64_t(-1) as float) as a max value. Fixes: 0fd43597 ("iris/perf: implement routines to return counter info") Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!5473>
00d3b138 -
Bas Nieuwenhuizen authored
Clashes with the SI definition. Closes: #3116 Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <!5673>
01986eaf -
Jonathan Marek authored
Accidentally broke this when rebasing the offending commit. My use case with non-zero explicit offset is UV plane of UBWC NV12, and only the UBWC slice offset is used for the UBWC sampler, so I didn't catch it immediately. Fixes: d53dc6c3 ("freedreno/fdl6: rework layout code a bit (reduce linear align to 64 bytes)") Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Part-of: <!5761>
3c5512ce -
Jonathan Marek authored
The previous version assumes tess level outputs will only be written once in the shader, however its not possible to guarantee that. It also assumes all invocations will write all the levels, which is also not guaranteed. This is required to fix the "tesselation" and "terraintessellation" demos with turnip. The comment about nir_lower_io_to_temporaries in lower_tess_ctrl_block is removed because nir_lower_io_to_temporaries specifically skips TESS_CTRL shaders so the comment doesn't make sense. The split load for tess levels workaround is removed, the new version only has scalar access unless if ever gets vectorized. This sets NIR_COMPACT_ARRAYS cap to avoid the glsl tess vec lowering with gallium. It seems this will also disable "LowerCombinedClipCullDistance", which I'm not sure was needed or not. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Part-of: <!5744>
b76c6dcb -
Jonathan Marek authored
This reverts commit d2df0761. The option is not used by any driver. Part-of: <!5744>
2044bdac -
Jonathan Marek authored
This reverts commit d2d4677b. The option is not used by any driver. Part-of: <!5744>
8453d294 -
Samuel Pitoiset authored
Fixes: 96063100 "radv: enable shaderStorageImageMultisample feature on GFX8+" Closes: #3219 Closes: #855 Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!3165>
7b21ce40 -
Bas Nieuwenhuizen authored
Seems like we forgot to set it all this time ... Fixes: b1444c9c "radv: Implement VK_ANDROID_native_buffer." Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!5759>
ad151499 -
Bas Nieuwenhuizen authored
We have an issue with early depth testing and discard, where non-perfect counts count the tile if the early depth test succeeds. We could spend a lot of effort to set this conditionally based on the presence of the two conditions, but in the presence of inherited queries let's try this first. Changing PERFECT_ZPASS_COUNTS since I'm pretty sure this has a lower performance impact than always using late depth testing. CC: <mesa-stable@lists.freedesktop.org> Closes: mesa/mesa#3218 Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!5757>
ad913a18 -
Bas Nieuwenhuizen authored
This reverts commit 7a5e6fd2. Since we have two different users bisecting issues to this commit, let's revert. Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Fixes: 7a5e6fd2 "radv: add support for MRTs compaction to avoid holes" Closes: #3202 Closes: #3228 (Other report in #3151 (comment 558589)) Part-of: <!5758>
c5d8961b -
Faith Ekstrand authored
This was causing vkAcquireNextImageKHR to not signal the fences and semaphores. In the case where the semaphore was brand new, this could cause an unsignalled syncobj to be passed into execbuffer2 which it will reject with -EINVAL leading to VK_ERROR_DEVICE_LOST. Thanks to Henrik Rydgård who works on the PPSSPP project for helping me figure this out. Fixes: ca3cfbf6 "vk: Add an initial implementation of the actual..." Fixes: 778b51f4 "vulkan/wsi: Add a hooks for signaling semaphores..." Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <!5672>
b0bbb623 -
Faith Ekstrand authored
Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <!5672>
85761e23 -
Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5762>
9c34a332 -
Rob Clark authored
Previously we would match the start of the compatible string, in a couple of cases, in order to match compatible strings like "qcom,adreno-630.2". But these cases would always list a more generic compatible (ie. "qcom,adreno") as a later choice. So if we parse all the compatible strings, we can do a more precise exact match. This avoids us accidentially matching on "qcom,adreno-smmu" and the hilarity that ensues. Fixes: 5a135071 ("freedreno/perfcntrs: add fdperf") Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5762>
385d036f -
Rob Clark authored
Avoid inadvertantly becoming master if fdperf happens to be the first thing to open the device. Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5762>
0a7b1f91 -
Jonathan Marek authored
Document this new a6xx_state_src value seen in A640/A650 tess traces. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Part-of: <!5760>
6d8e2cec -
Connor Abbott authored
Add the possibility to specify the source components. This is necessary to let the UBO/SSBO index have more than one component, and it also lets us remove a few hand-rolled load intrinsic definitions. Acked-by:
Jason Ekstrand <jason@jlekstrand.net> Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Part-of: <!5683>
7ab73160 -
Connor Abbott authored
For turnip, we use the "bindless" model on a6xx. Loads and stores with the bindless model require a bindless base, which is an immediate field in the instruction that selects between 5 different 64-bit "bindless base registers", a 32-bit descriptor index that's added to the base, and the usual 32-bit offset. The bindless base usually, but not always, corresponds to the Vulkan descriptor set. We can handle the case where the base is non-constant by using a bunch of if-statements, to make it a little easier in core NIR, and this seems to be what Qualcomm's driver does too. Therefore, the pointer format we need to use in NIR has a vec2 index, for the bindless base and descriptor index. Plumb this format through core NIR. Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Reviewed-by:
Kristian H. Kristensen <hoegsberg@google.com> Part-of: <!5683>
12e18d9e -
Ilia Mirkin authored
Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5753>
00f9d4b1 -
Ilia Mirkin authored
For some reason, in order to get all tests to pass, pretty much all hardware (across vendors) has to program in offset_units * 2. This fixes dEQP-GLES3.functional.polygon_offset.float32_displacement_with_units. While we're at it, add polygon offset clamp support. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!5763>
42c81415 -
Christian Gmeiner authored
As we do not support stream output buffers we only count the primitives processed by the pipeline. Use the correct query type. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by:
Lucas Stach <l.stach@pengutronix.de> Part-of: <!5754>
01a1926f -
Ilia Mirkin authored
Both vertex and fragment shaders need to have the lowering. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5751>
fc944428 -
Faith Ekstrand authored
Gallium drivers should never see nir_var_uniform because gallium lowers regular uniforms to a UBO. No GL driver should ever see either nir_var_mem_shared because that's lowered in GLSL IR. Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <!5418>
36a90468 -
Faith Ekstrand authored
Gallium drivers should never see nir_var_uniform because gallium lowers regular uniforms to a UBO. No GL driver should ever see either nir_var_mem_shared because that's lowered in GLSL IR. Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <!5418>
4f521e59 -
Faith Ekstrand authored
Gallium drivers should never see nir_var_uniform because gallium lowers regular uniforms to a UBO. No GL driver should ever see either nir_var_mem_shared because that's lowered in GLSL IR. Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <!5418>
786325fd -
Faith Ekstrand authored
Gallium drivers should never see nir_var_uniform because gallium lowers regular uniforms to a UBO. No GL driver should ever see either nir_var_mem_shared because that's lowered in GLSL IR. Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <mesa/mesa!5418>
96d99f2e -
Faith Ekstrand authored
Gallium drivers should never see nir_var_uniform because gallium lowers regular uniforms to a UBO. No GL driver should ever see either nir_var_mem_shared because that's lowered in GLSL IR. Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <!5418>
23b70948 -
Faith Ekstrand authored
Gallium drivers should never see nir_var_uniform because gallium lowers regular uniforms to a UBO. No GL driver should ever see either nir_var_mem_shared because that's lowered in GLSL IR. Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <!5418>
b019b22c -
Faith Ekstrand authored
Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <!5418>
be96b069 -
Faith Ekstrand authored
No drivers are using this anymore so we can delete it and not keep maintaining this legacy code-path. If any drivers want this in the future, they should use nir_lower_varst_to_explicit_types followed by nir_lower_explicit_io. Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <!5418>
0bc5a829 -
Faith Ekstrand authored
Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Part-of: <!5418>
a6ed1d7f -
Ilia Mirkin authored
This is necessary now that the compiler respects centroid interpolation, even in non-MSAA mode. Otherwise the interpolation doesn't work. Fixes a bunch of dEQP centroid transform feedback tests. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Rob Clark <robdclark@chromium.org> Part-of: <!5778>
bffee01b -
Marcin Ślusarz authored
perf_cfg is enough - it already contains almost all necessary information and is constructed in a more optimal way (O(n) vs O(n^2) - it uses hash table to build the unique counter list). "Almost all", because it doesn't contain OA raw counters, but we should have not exposed them anyway. Quoting Mark Janes: "I see no reason to include the OA raw counters in the list that are provided to the user. They are unusable. The MDAPI library can be used to configure raw counters in a way that provides esoteric metrics, but that library is written against INTEL_performance_query." Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Mark Janes <mark.a.janes@intel.com> Part-of: <!5399>
9f196625 -
Marcin Ślusarz authored
Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Mark Janes <mark.a.janes@intel.com> Part-of: <!5399>
3144bc1d -
Neil Roberts authored
The line coord is a coordinate along the axis perpendicular to the line. It is in the range [0,1] between the two edges of the line. It is available at least on Broadcom hardware. Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <!5624>
14dd65bb -
Neil Roberts authored
The line coord intrinsic is loaded from the implicit varying stored in the same slot as the point coord when drawing lines. Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <!5624>
2c461636 -
Neil Roberts authored
The first intrinsic is intended to expose the value set by glLineWidth to shaders internally. The second intrinsic exposes the value actually sent to the hardware. This may be wider than the first one in order to implement anti-aliasing. These will be used in later patches to implement a line smoothing lowering pass. v2: Add a second intrinsic for the expanded line width for anti-aliasing. Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <!5624>
121b82f6 -
Neil Roberts authored
Adds new QUNIFORMs to store the line widths. v2: Also handle the aa_line_width intrinsic Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <!5624>
207da33a -
Neil Roberts authored
When line smoothing is enabled, the driver now increases the width of the line so that it can add some semi-transparent pixels to either side of the line. A lowering pass is added which modifies the alpha component of every write to fragment output 0 so that if the fragment is outside the width of the line then the alpha is reduced. It additionally discards fragments that are completely invisible. It might seem bad to use discard on a tiled renderer but the assumption is that any bad effects from using discard will also happen anyway because of enabling alpha blending. v2: Disable the line smoothing pass entirely when the framebuffer contains an integer colour output or one with no alpha channel. Calculate the coverage once upfront and store in a global variable instead of calculating each time an output write is modified. Also do the conditional discard once upfront. v3: Don’t check whether the output buffer has an alpha channel. Only look at output 0. Use aa_line_width intrinsic instead of calculating the real line width in the shader. Clamp the coverage as part of the global variable, not per output write. Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <!5624>
ee4d51f8 -
Neil Roberts authored
V3D has a bit to set the line caps to be perpendicular to the line rather than aligned to the edges of the framebuffer. I don’t know what the disadvantages are of enabling this, but I noticed by experimentation that enabling line smoothing on the Intel driver also enables nicer line caps, so it seems nice to enable it here too. Reviewed-by:
Eric Anholt <eric@anholt.net> Part-of: <!5624>
137d8f98 -
Lionel Landwerlin authored
If we don't garbage collect the timeline, the value never progresses even though work completed. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Closes: #3226 Fixes: 34f32a6d ("anv: implement VK_KHR_timeline_semaphore") Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <!5774>
edc8119d -
Connor Abbott authored
Don't lower to offsets, instead use nir_lower_explicit_io here and use actual pointers for UBO's and SSBO's. This makes KHR_variable_pointers trivial. This also fixes asserts with shared variables, which are now supposed to be lowered with nir_lower_explicit_io. Part-of: <!5684>
9aec89ea -
Connor Abbott authored
Passes dEQP-VK.spirv_assembly.instruction.graphics.variable_pointers.* and dEQP-VK.spirv_assembly.instruction.compute.variable_pointers.* Part-of: <!5684>
7682c887 -
Chris Forbes authored
Fixes dEQP-GLES2.functional.shaders.conversions.scalar_to_scalar.float_to_int_fragment Signed-off-by:
Chris Forbes <chrisforbes@google.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!5779>
f6aa0719
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- .gitlab-ci.yml 1 addition, 0 deletions.gitlab-ci.yml
- .gitlab-ci/deqp-freedreno-a630-fails.txt 0 additions, 1 deletion.gitlab-ci/deqp-freedreno-a630-fails.txt
- .gitlab-ci/deqp-virgl-gl-fails.txt 1 addition, 2 deletions.gitlab-ci/deqp-virgl-gl-fails.txt
- .gitlab-ci/piglit/glslparser.txt 14 additions, 17 deletions.gitlab-ci/piglit/glslparser.txt
- .gitlab-ci/piglit/quick_gl.txt 6 additions, 7 deletions.gitlab-ci/piglit/quick_gl.txt
- .gitlab-ci/piglit/quick_shader.txt 15 additions, 477 deletions.gitlab-ci/piglit/quick_shader.txt
- docs/features.txt 11 additions, 11 deletionsdocs/features.txt
- docs/relnotes/new_features.txt 1 addition, 1 deletiondocs/relnotes/new_features.txt
- src/amd/addrlib/src/chip/gfx10/gfx10_gb_reg.h 1 addition, 1 deletionsrc/amd/addrlib/src/chip/gfx10/gfx10_gb_reg.h
- src/amd/addrlib/src/gfx10/gfx10addrlib.cpp 1 addition, 1 deletionsrc/amd/addrlib/src/gfx10/gfx10addrlib.cpp
- src/amd/compiler/aco_instruction_selection.cpp 6 additions, 12 deletionssrc/amd/compiler/aco_instruction_selection.cpp
- src/amd/vulkan/radv_android.c 2 additions, 0 deletionssrc/amd/vulkan/radv_android.c
- src/amd/vulkan/radv_cmd_buffer.c 24 additions, 1 deletionsrc/amd/vulkan/radv_cmd_buffer.c
- src/amd/vulkan/radv_meta.h 19 additions, 0 deletionssrc/amd/vulkan/radv_meta.h
- src/amd/vulkan/radv_nir_to_llvm.c 2 additions, 1 deletionsrc/amd/vulkan/radv_nir_to_llvm.c
- src/amd/vulkan/radv_pipeline.c 23 additions, 28 deletionssrc/amd/vulkan/radv_pipeline.c
- src/amd/vulkan/radv_shader_info.c 12 additions, 0 deletionssrc/amd/vulkan/radv_shader_info.c
- src/broadcom/Makefile.sources 1 addition, 0 deletionssrc/broadcom/Makefile.sources
- src/broadcom/compiler/meson.build 1 addition, 0 deletionssrc/broadcom/compiler/meson.build
- src/broadcom/compiler/nir_to_vir.c 18 additions, 1 deletionsrc/broadcom/compiler/nir_to_vir.c
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