- Sep 20, 2022
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Dylan Baker authored
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- Sep 19, 2022
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Tesscoord is declared as vec3 in the incoming shader but the z component of a tesscoord should only be referenced in the domain shader if the tessellator domain is of triangle type. Fixes vmx crash running GFXBench-Tessellation with MTL Renderer. Reviewed-by: Martin Krastev <krastevm@vmware.com> Reviewed-by: Min-Yu Huang <min-yuhuang@vmware.com> (cherry picked from commit f73862d3) Part-of: <mesa/mesa!18235>
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- Sep 16, 2022
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It doesn't work. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (cherry picked from commit a6050a43) Part-of: <mesa/mesa!18500>
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- Sep 15, 2022
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cc: mesa-stable Acked-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!18118> (cherry picked from commit 2fa5afd6)
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these come in as yoffset, but the constant data must use 0 since the sampler view is created with the offset cc: mesa-stable Acked-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!18118> (cherry picked from commit cd07a000)
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Cc: mesa-stable Part-of: <mesa/mesa!18076> (cherry picked from commit 163390d7)
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Some ASICs with gfx9 use compute rings for render. Fixes: 983223de - ac/gpu_info: use the kernel-reported GFX IP version to set gfx_level -v2: update merge requests num Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!18553> (cherry picked from commit fe8e18c7)
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The logic was inverted, we don't need aligned for later gens. Fixes: 60912f1e ("freedreno: we don't need aligned vbo's") Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!18605> (cherry picked from commit 2664d59a)
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Dylan Baker authored
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if the swapchain image is acquired in a different cmdbuf than it gets presented with, the acquire semaphore will have already been submitted by this point, and the swapchain should be flagged as such cc: mesa-stable Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <mesa/mesa!18557> (cherry picked from commit db192c08)
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We don't know how many descriptors will actually be valid, which could lead to preloading descriptors out-of-bounds of the descriptor size. This was leading to GPU hangs on some tests once we enabled inline uniforms. Fixes: d9fcf5de ("turnip: Enable nonuniform descriptor indexing") Part-of: <mesa/mesa!17960> (cherry picked from commit 15f3274e)
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`kill` changes which fibers are active, thus reodering instructions which depend on which fibers are active - is wrong. The issue was hidden because only `ballot(true)` is translated to movmsk immidiately, while others are passed as MACRO and don't properly take part in ir3_sched (which does the reordering). Closes: mesa/mesa#7162 Fixes CTS test (on gen3+): dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.subgroup_ballot Fixes: b1b80c06 ("ir3: Implement nir subgroup intrinsics") Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <mesa/mesa!18413> (cherry picked from commit 33e60798)
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The first argument is the name of the library, and the second argument is the list of files; those two got a bit mixed up. Fixes: 1ae8018a ("meson: Add support for the vc4 driver.") Fixes: 4f3e380f ("meson: Add support for the vc5 driver.") Signed-off-by: Eric Engestrom <eric@igalia.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!18593> (cherry picked from commit 5bfca00d)
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TEST: no segfault in dEQP-VK.api.command_buffers.bad_inheritance_info_random Fixes: 6f5289df ("venus: refactor VkCommandBufferBeginInfo fixups to function") Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org> Part-of: <mesa/mesa!18583> (cherry picked from commit e9b995ec)
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This is only needed on chips with tcc_rb_non_coherent=1. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Closes: mesa/mesa#7084 Cc: mesa-stable Part-of: <mesa/mesa!18494> (cherry picked from commit 07a520f7)
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This can be very slow on dGPU. I tried a different version that would allocate a full row and then do a single memcpy per row but the performance was similar so I kept the simple version. Cc: mesa-stable Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!18484> (cherry picked from commit a5b1a811)
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This is so dumb. Panfrost port of d98b82a1 ("iris/cs: take buffer offsets into account for CL") Fixes buffer.sub_buffers_read_write Fixes: 80b90a0f ("panfrost: Implement panfrost_set_global_binding") Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Suggested-by: Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!18560> (cherry picked from commit b4dd1b89)
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OpenGL 3.0 requires RGTC support, and until we have emulation in place, we should document that requirement. Fixes: d50e8554 ("zink: add feature-documentation") Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!18549> (cherry picked from commit 3454ff21)
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From the Vulkan spec 1.3.227: "If pipelineStageCreationFeedbackCount is not 0, pPipelineStageCreationFeedbacks must be a valid pointer to an array of pipelineStageCreationFeedbackCount VkPipelineCreationFeedback structures." Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!18513> (cherry picked from commit 28af93ac)
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Similar to how other I/O info is cleared at the beginning of gather_info we should also clear the cross-invocation mesh shader output mask. Fixes: 112a8568 Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <mesa/mesa!18464> (cherry picked from commit e58a5cca)
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For in-fence handling, dri2 has this below sequence in a row: 1. create_fence_fd: import external fence fd 2. fence_server_sync: import the pipe fence into the driver ctx 3. fence_reference: deref the created pipe fence Before this change, zink pushed the wrapped external semaphore to the wait semaphores of the next batch but the followed fence_reference will destroy the imported semaphore immediately. Instead of extending the lifecycle of the pipe fence throughout the batch state, we can simply transfer the semaphore ownership to the batch and destroy it upon batch reset. Fixes: 32597e11 ("zink: implement GL semaphores") Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org> Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!18453> (cherry picked from commit 6d1e2142)
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This change fixes below: 1. Dup the fence fd, otherwise, since external semaphore import takes the ownership of the fd, non-Vulkan part touches the fd leading to undefined behavior. This can be hit on implementations that defer the processing of the passed fd. 2. Use VK_SEMAPHORE_IMPORT_TEMPORARY_BIT for importing since that's required for SYNC_FD handle type because of its copy transference. Meanwhile, doing temporary import for opaque fd is fine in this path. Fixes: 32597e11 ("zink: implement GL semaphores") Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org> Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!18453> (cherry picked from commit c1b827d6)
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this ensures types which consume more than 1 slot are effectively tagged so that the next stage inputs are also assigned properly fixes: spec@arb_enhanced_layouts@execution@component-layout@vs-fs-array-dvec3 cc: mesa-stable Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <mesa/mesa!18444> (cherry picked from commit a0f6fecc)
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The change didn't make any sense. `s` will always be `NV50_SHADER_STAGE_COMPUTE`, because it's used to loop over all shader stages. And the TSC cache on the compute side is already flushed in `nv50_compute_validate_samplers`. Fixes spurious `CACHE_ERROR` dmesg messages. Fixes: ba6ba8c9 ("nv50: adapt texture and constbuf paths for compute shaders") Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: M Henning <drawoc@darkrefraction.com> Part-of: <mesa/mesa!18382> (cherry picked from commit 54709efd)
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When an OP_UNION def takes part in a vector source e.g. for a tex instruction we failed to clean up the OP_UNION instruction as rep() points towards the coalesced value instead. This fixes a regression on nv50 moving to NIR, but also potentially issues with nvc0. The main reason this is common in nv50 is, that we lower OP_SLCT to a set, predicated movs and a union. Closes: mesa/mesa#6406 Closes: mesa/mesa#7117 Cc: mesa-stable Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: M Henning <drawoc@darkrefraction.com> Part-of: <mesa/mesa!18377> (cherry picked from commit b23b94fb)
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The kernel driver has a range of valid priority values that can be supplied to it, submitting any priority value outside these bounds will result in `-EINVAL`. To avoid this, the priority value is now clamped to the range that the kernel supports. Fixes: 0c6fbfca Signed-off-by: Mark Collins <mark@igalia.com> Part-of: <mesa/mesa!18389> (cherry picked from commit c82249aa)
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Some claims of corruption, modifier-less Mesa already doesn't do it. Since these modifiers have no purpose besides being displayed lets just disable in Mesa. Cc: mesa-stable Tested-by: Michel Dänzer <mdaenzer@redhat.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!18140> (cherry picked from commit ae7532e0)
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Going to be a bad time if they disagree, which is bound to happen sometimes. Not asserting and stuff tends to be a better experience than crashing. Cc: mesa-stable Tested-by: Michel Dänzer <mdaenzer@redhat.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!18140> (cherry picked from commit af4b6568)
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These pci-ids should be included in mesa/mesa!14523, since these pci-ids will only be supported by kernels that support the forked Linux uapi. (Note that !14523 will never be merged into upstream Mesa.) Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc3#n695 Fixes: 398a9be9 ("intel/dev: Enable remaining DG2 and ATS-M device IDs") Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!18386> (cherry picked from commit b26980a4)
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Fixes: 6601e5d6 ("anv: implement VK_EXT_pipeline_creation_feedback") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!18451> (cherry picked from commit 92ee2e6b)
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The Vulkan spec states that it's illegal to pass a mipLodBias larger than maxSamplerLodBias, but the gallium value here hasn't been clamped. Closes: mesa/mesa#7140 Cc: mesa-stable Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!18295> (cherry picked from commit c551bb32)
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This fixes a buffer corruption bug with glMultiDrawElementsEXT(): the offset for the source index buffer is reset for each draw_multi slot, copying only the first `dr` values to each slot's index buffer. Cc: mesa-stable Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!18189> (cherry picked from commit b830091c)
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If a glMultiDrawElementsEXT() call doesn't fit into a single slot, the same pipe_resource pointer is copied into all following slots, the completion of each will decrement the reference counter; however, it was never incremented for all but the first slot. This fixes a use-after-free bug with glMultiDrawElementsEXT(). Cc: mesa-stable Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!18189> (cherry picked from commit 0a0fb7cb)
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They should cancel each other. Fixes: dEQP-GLES2.functional.shaders.random.basic_expression.combined.0 Fixes: 28801b48 ("agx: Add forward optimizing pass for fmov") Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <mesa/mesa!18380> (cherry picked from commit 095415cd)
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The only reason why we didn't notice before is because ANV always re-emits all scissors and viewports if the count changes. Fixes: fcedb125 ("vulkan: Add a common data structure for dynamic states") Part-of: <mesa/mesa!18160> (cherry picked from commit 6ffbb1ab)
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If an instruction has multiple destinations and *any* of them are needed by helper invocations, we should keep helper invocations alive. This is a bug fix. Consider the GLSL: first = texture(sampler, ...); float res = texture(sampler, vec2(first.y)).x + first.x; Corresponding to the IR: first = ... x, y, z, w = SPLIT first second = TEX y, y x', y', z', w' = SPLIT second FADD res, x, x' Here, x is not required by helper invocations (the coordinates to TEX) while y is required. If we only look at only the first destinations, we incorrectly decide that first is not required and fail to set the .skip bit, leading to incorrect results. Fixes: 5febeae5 ("pan/bi: Emit collect and split") Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!17794> (cherry picked from commit d0aaf526)
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...with dual source blending. Fixes shaders/dolphin/smg.1.shader_test There are more IR sources than Valhall machine sources here. Fixes: b48933d6 ("pan/va: Include BLEND for va_swap_12") Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!17794> (cherry picked from commit b5a6375f)
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Fixes: 91dcadf9 ("llvmpipe: finish rendering before flushing frontbuffer resources.") Reviewed-by: Jose Fonseca <jfonseca@vmware.com> Part-of: <mesa/mesa!18392> (cherry picked from commit 7437c8f7)
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The GLSL code sequence: texture2D(tex0, u_coords) + texture2D(tex1, u_coords) will be optimized to TEXC_DUAL tex0/tex1, u_coords, #texture_descriptor If this optimization happens after lowering FAU, the resulting TEXC instruction is unschedulable: both the uniform and the constant descriptor fight for the same FAU slot. However, if this optimization happens before lowering FAU, then the FAU lowering will move the descriptor into a register, complicating the dual texturing fixup in RA. To fix this interaction, fuse dual texturing before lowering FAU and keep texture descriptors as constants when lowering FAU of TEXC. Fixes scheduling failure in piglit drawoverhead -test 3 with uniform reordering. Fixes: a4d3a296 ("pan/bi: Enable dual texture fusing pass") Fixes: 6b2eda6b ("pan/bi: Reorder pushed uniforms to avoid moves") Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!18378> (cherry picked from commit c5b9a01f)
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This motherboard-down pci-id was added in kernel commit 8618b8489ba6 ("drm/i915: DG2 and ATS-M device ID updates"). Ref: bspec 44477 Ref: https://patchwork.freedesktop.org/patch/msgid/20220701152231.529511-2-matthew.d.roper@intel.com Fixes: ad565f6b ("intel/dev: Enable first set of DG2 PCI IDs") Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!18385> (cherry picked from commit 65c9a810)
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