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Commits on Source (22)
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Alex Deucher authored
There are a number of systems and cloud providers out there that have nomodeset hardcoded in their kernel parameters to block nouveau for the nvidia driver. This prevents the amdgpu driver from loading. Unfortunately the end user cannot easily change this. The preferred way to block modules from loading is to use modprobe.blacklist=<driver>. That is what providers should be using to block specific drivers. Drop the check to allow the driver to load even when nomodeset is specified on the kernel command line. Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Move to probe so we can check the PCI device type and only apply the drm_firmware_drivers_only() check for PCI DISPLAY classes. Also add a module parameter to override the nomodeset kernel parameter as a workaround for platforms that have this hardcoded on their kernel command lines. Reviewed-by:
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Alex Deucher authored
PCI_CLASS_ACCELERATOR_PROCESSING devices won't ever be the sysfb, so there is no need to free conflicting apertures. Reviewed-by:
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Tao Zhou authored
Clear old data and save it in V3 format. v2: only format eeprom data for new ASICs. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Kenneth Feng authored
Shorten the gfx idle worker timeout. This is to sync with DAL when there is no activity on the screen. Original 1 second can not sync with DAL, so DAL can not apply MALL when the workload type is not bootup default. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Xiang Liu authored
The mistake of computation for remain size of CPER ring will cause unbreakable while cycle when CPER ring overflow. Signed-off-by:
Xiang Liu <xiang.liu@amd.com> Reviewed-by:
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Dominik Kaszewski authored
HDCP Locality Check is being moved to FW, add debug flags to control its behavior in existing hardware for validation purposes. Signed-off-by:
Dominik Kaszewski <dominik.kaszewski@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Alex Hung authored
[WHAT & HOW] dp_is_128b_132b_signal dereferences pipe->stream so it is necessary to check it in advance. Also fix erroneous spaces and move a variable declaration to top. Reviewed-by:
Alex Hung <alex.hung@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Ryan Seto authored
[WHY & HOW] Fixed Overflow issue by clamping VStartup to max value of register. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
Ryan Seto <ryanseto@amd.com> Signed-off-by:
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Jing Zhou authored
[WHY] We should never apply a minimum dispclk value while in prepare_bandwidth or while displays are active. This is always an optimizaiton for when all displays are disabled. [HOW] Defer dispclk optimization until safe_to_lower = true and display_count reaches 0. Since 0 has a special value in this logic (ie. no dispclk required) we also need adjust the logic that clamps it for the actual request to PMFW. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Chris Park <chris.park@amd.com> Reviewed-by:
Eric Yang <eric.yang@amd.com> Signed-off-by:
Jing Zhou <Jing.Zhou@amd.com> Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Yilin Chen authored
[WHY] The info message was wrong when support_edp0_on_dp1 is enabled [HOW] Use correct info message for support_edp0_on_dp1 Fixes: f6d17270 ("drm/amd/display: add a quirk to enable eDP0 on DP1") Reviewed-by:
Yilin Chen <Yilin.Chen@amd.com> Signed-off-by:
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Cruise Hung authored
[WHY & HOW] The response of DP BW allocation is handled in Outbox ISR. When it failed to request the DP BW allocation, it sent another DPCD request in Outbox ISR immediately. The DP AUX reply also uses the Outbox ISR. So, no AUX reply happened in this case. Change to use HPD IRQ for the notification. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
Cruise Hung <Cruise.Hung@amd.com> Signed-off-by:
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Dillon Varone authored
This reverts commit 15d1c2e6. Reason: Cursor movement causes system to hang. Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Mario Limonciello authored
[WHY] DMUB locking is important to make sure that registers aren't accessed while in PSR. Previously it was enabled but caused a deadlock in situations with multiple eDP panels. [HOW] Detect if multiple eDP panels are in use to decide whether to use lock. Refactor the function so that the first check is for PSR-SU and then replay is in use to prevent having to look up number of eDP panels for those configurations. Fixes: f245b400 ("Revert "drm/amd/display: Use HW lock mgr for PSR1"") Closes: drm/amd#3965 Reviewed-by:
ChiaHsuan Chung <chiahsuan.chung@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Lo-an Chen authored
[WHY] The fw_state in dmub_srv was assigned with wrong address. The address was pointed to the firmware region. [HOW] Fix the firmware state by using DMUB_DEBUG_FW_STATE_OFFSET in dmub_cmd.h. Reviewed-by:
Lo-an Chen <lo-an.chen@amd.com> Signed-off-by:
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Charlene Liu authored
[WHY] Update the static soc table dcn3_5_soc. Reviewed-by:
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Charlene Liu authored
[WHY] Not like dppclk/dispclk, dml2 will calculate the minimum required clocks. For dscclk, it is used for pure comparision. Reviewed-by:
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Taimur Hassan authored
This version brings along following fixes: - Use DPM table clk setting for dml2 soc dscclk - Update static soc table - Fix incorrect fw_state address in dmub_srv - Use HW lock mgr for PSR1 when only one eDP - Revert "Support for reg inbox0 for host->DMUB CMDs" - Change notification of link BW allocation - Fix message for support_edp0_on_dp1 - Guard against setting dispclk low for dcn31x - Prevent VStartup Overflow - Check pipe->stream before passing it to a function Acked-by:
Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by:
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fcui authored
Free on driver cleanup. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Flora Cui <flora.cui@amd.com> Signed-off-by:
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Tomasz Pakuła authoredCurrently, it seems like the code was carried over from RDNA3 because it assumes two possible values to set. RDNA4, instead of having: 0: min SCLK 1: max SCLK only has 0: SCLK offset This change makes it so it only reports current offset value instead of showing possible min/max values and their indices. Moreover, it now only accepts the offset as a value, without the indice index. Additionally, the lower bound was printed as %u by mistake. Old: OD_SCLK_OFFSET: 0: -500Mhz 1: 1000Mhz OD_MCLK: 0: 97Mhz 1: 1259MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK_OFFSET: -500Mhz 1000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -200mv 0mv New: OD_SCLK_OFFSET: 0Mhz OD_MCLK: 0: 97Mhz 1: 1259MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK_OFFSET: -500Mhz 1000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -200mv 0mv Setting this offset: Old: "s 1 <offset>" New: "s <offset>" Closes: drm/amd#4036 Reviewed-by:
Tomasz Pakuła <tomasz.pakula.oficjalny@gmail.com> Signed-off-by:
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Jie1zhang authored
The scheduler should restart only if the reset operation succeeds This ensures that new tasks are only submitted to the queues after a successful reset. Fixes: 4c02f730 ("drm/amdgpu: Introduce conditional user queue suspension for SDMA resets") Suggested-by:
Jesse.Zhang <Jesse.zhang@amd.com> Reviewed-by:
Tim Huang <tim.huang@amd.com> Signed-off-by:
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lijo lazar authored
XGMI and WAFL share the same versions. Use WAFL version if XGMI version is not present in discovery. Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
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- drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c 8 additions, 7 deletionsdrivers/gpu/drm/amd/amdgpu/amdgpu_cper.c
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 14 additions, 4 deletionsdrivers/gpu/drm/amd/amdgpu/amdgpu_device.c
- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 9 additions, 4 deletionsdrivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 14 additions, 3 deletionsdrivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 2 additions, 2 deletionsdrivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 7 additions, 0 deletionsdrivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c 14 additions, 12 deletionsdrivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h 1 addition, 0 deletionsdrivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c 1 addition, 1 deletiondrivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 1 addition, 1 deletiondrivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c 12 additions, 8 deletions...rs/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c 10 additions, 3 deletions...rs/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c 6 additions, 9 deletionsdrivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
- drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c 2 additions, 7 deletionsdrivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
- drivers/gpu/drm/amd/display/dc/dc.h 2 additions, 16 deletionsdrivers/gpu/drm/amd/display/dc/dc.h
- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 85 additions, 100 deletionsdrivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h 1 addition, 1 deletiondrivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
- drivers/gpu/drm/amd/display/dc/dc_helper.c 1 addition, 1 deletiondrivers/gpu/drm/amd/display/dc/dc_helper.c
- drivers/gpu/drm/amd/display/dc/dc_types.h 0 additions, 1 deletiondrivers/gpu/drm/amd/display/dc/dc_types.h
- drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c 1 addition, 2 deletionsdrivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c