RDNA4 `pp_od_clk_voltage` doesn't reflect current SCLK offset

Brief summary of the problem:

Changing the max SCLK offset on RDNA4 doesn't reflect in pp_od_clk_voltage. Moreover, it seems that the value there is always erroneous as it reports [1] 1000MHz instead of the default of 0MHz for this offset. I don't see any errors in dmesg related to this.

With RDNA4, we can only change the max clock offset, so maybe it would be better to hide [0] altogether or show the max SCLK offset as [0]? If that's possible of course.

Hardware description:

• CPU: Ryzen 7 5800X3D
• GPU: RX 9070 XT Hellhound
• System Memory: 64 GiB

System information:

• Distro name and Version: Arch Linux
• Kernel version: 6.13.6
• Custom kernel: N/A
• AMD official driver version: Mesa 25.0 + RADV 25.0

How to reproduce the issue:

cat /sys/class/drm/card1/device/pp_od_clk_voltage
sudo tee /sys/class/drm/card1/device/pp_od_clk_voltage <<<"s 1 100"
sudo tee /sys/class/drm/card1/device/pp_od_clk_voltage <<<"c"
cat /sys/class/drm/card1/device/pp_od_clk_voltage

Attached files:

Screenshots/video files

I found that it only reports min and max now instead of reporting current value. This is probably because the code was copied and pasted?:

PPTable_t *pptable = smu->smu_table.driver_pptable;
const OverDriveLimits_t * const overdrive_upperlimits =
			&pptable->SkuTable.OverDriveLimitsBasicMax;
const OverDriveLimits_t * const overdrive_lowerlimits =
			&pptable->SkuTable.OverDriveLimitsBasicMin;

size += sysfs_emit_at(buf, size, "OD_SCLK_OFFSET:\n");
size += sysfs_emit_at(buf, size, "0: %dMhz\n1: %uMhz\n",
			overdrive_lowerlimits->GfxclkFoffset,
			overdrive_upperlimits->GfxclkFoffset);

I'm testing a patch right now. If it works nicely, I'll post it here.

Done. New behavior:

Click to expand

tomek@komputr ~ $ cat /sys/class/drm/card1/device/pp_od_clk_voltage
OD_SCLK_OFFSET:
0Mhz
OD_MCLK:
0: 97Mhz
1: 1259MHz
OD_VDDGFX_OFFSET:
0mV
OD_RANGE:
SCLK_OFFSET:    -500Mhz       1000Mhz
MCLK:      97Mhz       1500Mhz
VDDGFX_OFFSET:    -200mv          0mv

tomek@komputr ~ $ sudo tee /sys/class/drm/card1/device/pp_od_clk_voltage <<<"s 1 100"
s 1 100
tee: /sys/class/drm/card1/device/pp_od_clk_voltage: Invalid argument

tomek@komputr ~ $ sudo tee /sys/class/drm/card1/device/pp_od_clk_voltage <<<"s 100"  
s 100

tomek@komputr ~ $ sudo tee /sys/class/drm/card1/device/pp_od_clk_voltage <<<"c"    
c

tomek@komputr ~ $ cat /sys/class/drm/card1/device/pp_od_clk_voltage                  
OD_SCLK_OFFSET:
100Mhz
OD_MCLK:
0: 97Mhz
1: 1259MHz
OD_VDDGFX_OFFSET:
0mV
OD_RANGE:
SCLK_OFFSET:    -500Mhz       1000Mhz
MCLK:      97Mhz       1500Mhz
VDDGFX_OFFSET:    -200mv          0mv

tomek@komputr ~ $ sudo tee /sys/class/drm/card1/device/pp_od_clk_voltage <<<"s -100"
s -100

tomek@komputr ~ $ sudo tee /sys/class/drm/card1/device/pp_od_clk_voltage <<<"c"     
c

tomek@komputr ~ $ cat /sys/class/drm/card1/device/pp_od_clk_voltage                 
OD_SCLK_OFFSET:
-100Mhz
OD_MCLK:
0: 97Mhz
1: 1259MHz
OD_VDDGFX_OFFSET:
0mV
OD_RANGE:
SCLK_OFFSET:    -500Mhz       1000Mhz
MCLK:      97Mhz       1500Mhz
VDDGFX_OFFSET:    -200mv          0mv

Patch sent to the amdgpu mailing list. @agd5f I added you as CC. I'm attaching it here just if there are some issues with me sending to the ML.

drm-amdgpu-pm-Handle-SCLK-offset-correctly-in-overdr.patch

Is the amd-gfx mailing list filtered?

Patch was accepted and awaiting upstreaming. Closing

closed

mentioned in commit agd5f/linux@1cfeb60e

mentioned in commit agd5f/linux@d9d4cb22