Commits on Source (14)
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Nikita Zhandarovich authored
On the off chance that command stream passed from userspace via ioctl() call to radeon_vce_cs_parse() is weirdly crafted and first command to execute is to encode (case 0x03000001), the function in question will attempt to call radeon_vce_cs_reloc() with size argument that has not been properly initialized. Specifically, 'size' will point to 'tmp' variable before the latter had a chance to be assigned any value. Play it safe and init 'tmp' with 0, thus ensuring that radeon_vce_cs_reloc() will catch an early error in cases like these. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 2fc5703a ("drm/radeon: check VCE relocation buffer range v3") Signed-off-by:
Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 2d52de55) Cc: stable@vger.kernel.org
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David Rosca authored
1920x1088 is the maximum supported resolution. Signed-off-by:
David Rosca <david.rosca@amd.com> Acked-by:
Ruijing Dong <ruijing.dong@amd.com> Signed-off-by:
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David Rosca authored
8192x8192 is the maximum supported resolution. Signed-off-by:
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David Rosca authored
JPEG is only supported for VCN1+. Signed-off-by:
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Harish Kasiviswanathan authored
Expose unique_id for gfx12 Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
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Alex Deucher authored
Add callbacks for fan speed fetching. Closes: drm/amd#4034 Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Jay Cornwall authored
VALU instructions with SGPR source need wait states to avoid hazard with SALU using different SGPR. v2: Eliminate some hazards to reduce code explosion Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
Lancelot Six <lancelot.six@amd.com> Acked-by:
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Wentao Liang authored
In gfx_v12_0_cp_gfx_load_me_microcode_rs64(), gfx_v12_0_pfp_fini() is incorrectly used to free 'me' field of 'gfx', since gfx_v12_0_pfp_fini() can only release 'pfp' field of 'gfx'. The release function of 'me' field should be gfx_v12_0_me_fini(). Fixes: 52cb80c1 ("drm/amdgpu: Add gfx v12_0 ip block support (v6)") Signed-off-by:
Wentao Liang <vulab@iscas.ac.cn> Signed-off-by:
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David Belanger authored
Always use MTYPE_UC if UNCACHED flag is specified. This makes kernarg region uncached and it restores usermode cache disable debug flag functionality. Do not set MTYPE_UC for COHERENT flag, on GFX12 coherence is handled by shader code. Signed-off-by:
David Belanger <david.belanger@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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PhilipY authored
To workaround queue full h/w issue on Gfx7/8, when application create AQL queue, the ring buffer bo allocate size is queue_size/2 and map queue_size ring buffer to GPU in 2 pieces using 2 attachments, each attachment map size is queue_size/2, with same ring_bo backing memory. For Gfx7/8, user queue buffer validation should use queue_size/2 to verify ring_bo allocation and mapping size. Fixes: 68e599db ("drm/amdkfd: Validate user queue buffers") Suggested-by:
Tomáš Trnka <trnka@scm.com> Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Acked-by:
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Yilin Chen authored
[WHY] The info message was wrong when support_edp0_on_dp1 is enabled [HOW] Use correct info message for support_edp0_on_dp1 Fixes: f6d17270 ("drm/amd/display: add a quirk to enable eDP0 on DP1") Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Yilin Chen <Yilin.Chen@amd.com> Signed-off-by:
Alex Hung <alex.hung@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Mario Limonciello authored
[WHY] DMUB locking is important to make sure that registers aren't accessed while in PSR. Previously it was enabled but caused a deadlock in situations with multiple eDP panels. [HOW] Detect if multiple eDP panels are in use to decide whether to use lock. Refactor the function so that the first check is for PSR-SU and then replay is in use to prevent having to look up number of eDP panels for those configurations. Fixes: f245b400 ("Revert "drm/amd/display: Use HW lock mgr for PSR1"") Closes: drm/amd#3965 Reviewed-by:
ChiaHsuan Chung <chiahsuan.chung@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Lo-an Chen authored
[WHY] The fw_state in dmub_srv was assigned with wrong address. The address was pointed to the firmware region. [HOW] Fix the firmware state by using DMUB_DEBUG_FW_STATE_OFFSET in dmub_cmd.h. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Lo-an Chen <lo-an.chen@amd.com> Signed-off-by:
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Tomasz Pakuła authoredCurrently, it seems like the code was carried over from RDNA3 because it assumes two possible values to set. RDNA4, instead of having: 0: min SCLK 1: max SCLK only has 0: SCLK offset This change makes it so it only reports current offset value instead of showing possible min/max values and their indices. Moreover, it now only accepts the offset as a value, without the indice index. Additionally, the lower bound was printed as %u by mistake. Old: OD_SCLK_OFFSET: 0: -500Mhz 1: 1000Mhz OD_MCLK: 0: 97Mhz 1: 1259MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK_OFFSET: -500Mhz 1000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -200mv 0mv New: OD_SCLK_OFFSET: 0Mhz OD_MCLK: 0: 97Mhz 1: 1259MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK_OFFSET: -500Mhz 1000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -200mv 0mv Setting this offset: Old: "s 1 <offset>" New: "s <offset>" Closes: drm/amd#4036 Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
Tomasz Pakuła <tomasz.pakula.oficjalny@gmail.com> Signed-off-by:
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- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 1 addition, 1 deletiondrivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c 2 additions, 20 deletionsdrivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
- drivers/gpu/drm/amd/amdgpu/nv.c 10 additions, 10 deletionsdrivers/gpu/drm/amd/amdgpu/nv.c
- drivers/gpu/drm/amd/amdgpu/soc15.c 10 additions, 11 deletionsdrivers/gpu/drm/amd/amdgpu/soc15.c
- drivers/gpu/drm/amd/amdgpu/vi.c 18 additions, 25 deletionsdrivers/gpu/drm/amd/amdgpu/vi.c
- drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h 360 additions, 317 deletionsdrivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
- drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm 44 additions, 38 deletionsdrivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm
- drivers/gpu/drm/amd/amdkfd/kfd_queue.c 11 additions, 1 deletiondrivers/gpu/drm/amd/amdkfd/kfd_queue.c
- drivers/gpu/drm/amd/amdkfd/kfd_svm.c 1 addition, 7 deletionsdrivers/gpu/drm/amd/amdkfd/kfd_svm.c
- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 1 addition, 1 deletiondrivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c 11 additions, 0 deletionsdrivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
- drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c 1 addition, 1 deletiondrivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
- drivers/gpu/drm/amd/pm/amdgpu_pm.c 2 additions, 0 deletionsdrivers/gpu/drm/amd/pm/amdgpu_pm.c
- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c 53 additions, 41 deletionsdrivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
- drivers/gpu/drm/radeon/radeon_vce.c 1 addition, 1 deletiondrivers/gpu/drm/radeon/radeon_vce.c