- Mar 21, 2025
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Christian König authored
That was quite troublesome for gang submit. Completely drop this approach and enforce the isolation separately. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Instead of emitting the cleaner shader for every job which has the enforce_isolation flag set only emit it for the first submission from every client. v2: add missing NULL check v3: fix another NULL pointer deref Signed-off-by:
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Christian König authored
Limiting the number of available VMIDs to enforce isolation causes some issues with gang submit and applying certain HW workarounds which require multiple VMIDs to work correctly. So instead start to track all submissions to the relevant engines in a per partition data structure and use the dma_fences of the submissions to enforce isolation similar to what a VMID limit does. v2: use ~0l for jobs without isolation to distinct it from kernel submissions which uses NULL for the owner. Add some warning when we are OOM. Signed-off-by: -
Christian König authored
This allows using amdgpu_sync even without peeking into the fences for a long time. Signed-off-by:
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Christian König authored
In the critical submission path memory allocations can't wait for reclaim since that can potentially wait for submissions to finish. Finally clean that up and mark most memory allocations in the critical path with GFP_NOWAIT. The only exception left is the dma_fence_array() used when no VMID is available, but that will be cleaned up later on. Signed-off-by:
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Kenneth Feng authored
This reverts commit 55ff973f. Reason for revert: this causes some tests fail with call trace. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Ahmad Rehman authored
For SRIOV, skip the SDMA queue reset and return error. The engine/queue reset failure will trigger FLR in the sequence. v2: do not add queue reset support mask for sriov Signed-off-by:
Ahmad Rehman <Ahmad.Rehman@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Ahmad Rehman authored
Add case for 13.0.12. Signed-off-by:
Ahmad Rehman <ahrehman@amd.com> Reviewed-by:
<Vignesh.Chander@amd.com> Signed-off-by:
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Ellen Pan authored
This enables ras to be resumed after gpu recovery on mi350 sriov. Signed-off-by:
Ellen Pan <yunru.pan@amd.com> Reviewed-by:
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jokim-amd authored
Clause instructions with precise memory enabled currently hang the shader so set capabilities flag to disabled since it's unsafe to use for debugging. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Tested-by:
Lancelot Six <lancelot.six@amd.com> Reviewed-by:
Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by:
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- Mar 19, 2025
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Victor Skvortsov authored
VFs cannot read the NAK_COUNTER register. This information is only available through PMFW metrics. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by:
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Candice Li authored
Add active_umc_mask to ras init_flags. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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lijo lazar authored
Add description for debug_mask bit options. Signed-off-by:
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lijo lazar authored
In certain cases, it's desirable to avoid PMFW log transactions to system memory. Add a mask bit to decide whether to allocate smu pool in device memory or system memory. Signed-off-by:
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Alex Deucher authored
No need to make the workload profile setup dependent on the results of cancelling the delayed work thread. We have all of the necessary checking in place for the workload profile reference counting, so separate the two. As it is now, we can theoretically end up with the call from begin_use happening while the worker thread is executing which would result in the profile not getting set for that submission. It should not affect the reference counting. v2: bail early if the the profile is already active (Lijo) Reviewed-by:
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Alex Deucher authored
No need to make the workload profile setup dependent on the results of cancelling the delayed work thread. We have all of the necessary checking in place for the workload profile reference counting, so separate the two. As it is now, we can theoretically end up with the call from begin_use happening while the worker thread is executing which would result in the profile not getting set for that submission. It should not affect the reference counting. v2: bail early if the the profile is already active (Lijo) Reviewed-by:
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Candice Li authored
Add EEPROM I2C address support for smu v13_0_12. Signed-off-by:
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Alex Deucher authored
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count on submissions, but the decrement may be delayed as work comes in. Track when we enable the workload profile so the references are balanced. v2: switch to a mutex and active flag v3: fix mutex init Fixes: 1443dd3c ("drm/amd/pm: fix and simplify workload handling") Cc: Yang Wang <kevinyang.wang@amd.com> Cc: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Alex Deucher authored
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count on submissions, but the decrement may be delayed as work comes in. Track when we enable the workload profile so the references are balanced. v2: switch to a mutex and active flag v3: fix mutex init Fixes: 8fdb3958 ("drm/amdgpu/gfx: add ring helpers for setting workload profile") Cc: Yang Wang <kevinyang.wang@amd.com> Cc: Kenneth Feng <kenneth.feng@amd.com> Tested-by:
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Harish Kasiviswanathan authored
For certain ASICs where dequeue_wait_count don't need to be initialized, pm_config_dequeue_wait_counts_v9 return without filling in the packet information. However, the calling function interprets this as a success and sends the uninitialized packet to firmware causing hang. Fix the above bug by not calling pm_config_dequeue_wait_counts_v9 for ASICs that don't need the value to be initialized. v2: Removed redudant code. Tidy up code based on review comments v3: Don't call pm_config_dequeue_wait_counts_v9 for certain ASICs Fixes: ed962f8d ("drm/amdkfd: Add pm_config_dequeue_wait_counts API") Signed-off-by: -
FengWei authored
Use max3() macro instead of nesting max() to simplify the return statement. Signed-off-by:
FengWei <feng.wei8@zte.com.cn> Signed-off-by:
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Christian König authored
We keep the gang submission fence around in adev, make sure that it stays alive. v2: fix memory leak on retry Signed-off-by:
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- Mar 18, 2025
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lijo lazar authored
XGMI and WAFL share the same versions. Use WAFL version if XGMI version is not present in discovery. Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
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Jie1zhang authored
The scheduler should restart only if the reset operation succeeds This ensures that new tasks are only submitted to the queues after a successful reset. Fixes: 4c02f730 ("drm/amdgpu: Introduce conditional user queue suspension for SDMA resets") Suggested-by:
Jesse.Zhang <Jesse.zhang@amd.com> Reviewed-by:
Tim Huang <tim.huang@amd.com> Signed-off-by:
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Tomasz Pakuła authoredCurrently, it seems like the code was carried over from RDNA3 because it assumes two possible values to set. RDNA4, instead of having: 0: min SCLK 1: max SCLK only has 0: SCLK offset This change makes it so it only reports current offset value instead of showing possible min/max values and their indices. Moreover, it now only accepts the offset as a value, without the indice index. Additionally, the lower bound was printed as %u by mistake. Old: OD_SCLK_OFFSET: 0: -500Mhz 1: 1000Mhz OD_MCLK: 0: 97Mhz 1: 1259MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK_OFFSET: -500Mhz 1000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -200mv 0mv New: OD_SCLK_OFFSET: 0Mhz OD_MCLK: 0: 97Mhz 1: 1259MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK_OFFSET: -500Mhz 1000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -200mv 0mv Setting this offset: Old: "s 1 <offset>" New: "s <offset>" Closes: drm/amd#4036 Reviewed-by:
Tomasz Pakuła <tomasz.pakula.oficjalny@gmail.com> Signed-off-by:
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fcui authored
Free on driver cleanup. Reviewed-by:
Flora Cui <flora.cui@amd.com> Signed-off-by:
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Taimur Hassan authored
This version brings along following fixes: - Use DPM table clk setting for dml2 soc dscclk - Update static soc table - Fix incorrect fw_state address in dmub_srv - Use HW lock mgr for PSR1 when only one eDP - Revert "Support for reg inbox0 for host->DMUB CMDs" - Change notification of link BW allocation - Fix message for support_edp0_on_dp1 - Guard against setting dispclk low for dcn31x - Prevent VStartup Overflow - Check pipe->stream before passing it to a function Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Charlene Liu authored
[WHY] Not like dppclk/dispclk, dml2 will calculate the minimum required clocks. For dscclk, it is used for pure comparision. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Signed-off-by:
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Charlene Liu authored
[WHY] Update the static soc table dcn3_5_soc. Reviewed-by:
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Lo-an Chen authored
[WHY] The fw_state in dmub_srv was assigned with wrong address. The address was pointed to the firmware region. [HOW] Fix the firmware state by using DMUB_DEBUG_FW_STATE_OFFSET in dmub_cmd.h. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Lo-an Chen <lo-an.chen@amd.com> Signed-off-by:
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Mario Limonciello authored
[WHY] DMUB locking is important to make sure that registers aren't accessed while in PSR. Previously it was enabled but caused a deadlock in situations with multiple eDP panels. [HOW] Detect if multiple eDP panels are in use to decide whether to use lock. Refactor the function so that the first check is for PSR-SU and then replay is in use to prevent having to look up number of eDP panels for those configurations. Fixes: f245b400 ("Revert "drm/amd/display: Use HW lock mgr for PSR1"") Closes: drm/amd#3965 Reviewed-by:
ChiaHsuan Chung <chiahsuan.chung@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Dillon Varone authored
This reverts commit 15d1c2e6. Reason: Cursor movement causes system to hang. Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Cruise Hung authored
[WHY & HOW] The response of DP BW allocation is handled in Outbox ISR. When it failed to request the DP BW allocation, it sent another DPCD request in Outbox ISR immediately. The DP AUX reply also uses the Outbox ISR. So, no AUX reply happened in this case. Change to use HPD IRQ for the notification. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
Cruise Hung <Cruise.Hung@amd.com> Signed-off-by:
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Yilin Chen authored
[WHY] The info message was wrong when support_edp0_on_dp1 is enabled [HOW] Use correct info message for support_edp0_on_dp1 Fixes: f6d17270 ("drm/amd/display: add a quirk to enable eDP0 on DP1") Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Yilin Chen <Yilin.Chen@amd.com> Signed-off-by:
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Jing Zhou authored
[WHY] We should never apply a minimum dispclk value while in prepare_bandwidth or while displays are active. This is always an optimizaiton for when all displays are disabled. [HOW] Defer dispclk optimization until safe_to_lower = true and display_count reaches 0. Since 0 has a special value in this logic (ie. no dispclk required) we also need adjust the logic that clamps it for the actual request to PMFW. Reviewed-by:
Chris Park <chris.park@amd.com> Reviewed-by:
Eric Yang <eric.yang@amd.com> Signed-off-by:
Jing Zhou <Jing.Zhou@amd.com> Signed-off-by:
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Ryan Seto authored
[WHY & HOW] Fixed Overflow issue by clamping VStartup to max value of register. Reviewed-by:
Ryan Seto <ryanseto@amd.com> Signed-off-by:
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Alex Hung authored
[WHAT & HOW] dp_is_128b_132b_signal dereferences pipe->stream so it is necessary to check it in advance. Also fix erroneous spaces and move a variable declaration to top. Reviewed-by:
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Dominik Kaszewski authored
HDCP Locality Check is being moved to FW, add debug flags to control its behavior in existing hardware for validation purposes. Signed-off-by:
Dominik Kaszewski <dominik.kaszewski@amd.com> Reviewed-by:
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Xiang Liu authored
The mistake of computation for remain size of CPER ring will cause unbreakable while cycle when CPER ring overflow. Signed-off-by:
Xiang Liu <xiang.liu@amd.com> Reviewed-by:
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Kenneth Feng authored
Shorten the gfx idle worker timeout. This is to sync with DAL when there is no activity on the screen. Original 1 second can not sync with DAL, so DAL can not apply MALL when the workload type is not bootup default. Signed-off-by:
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