- Jun 01, 2022
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Dylan Baker authored
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Dylan Baker authored
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Otherwise, it would mutate `fneg(fadd(-0, 0))` into `fadd(0, -0)` which isn't correct since -0 + (+0) = +0 + (-0) = +0. This fixes the OpenCL contraction tests on Iris. Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!16041> (cherry picked from commit df1876f6)
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this is not required by any version of GL, so don't pretend it's needed cc: mesa-stable Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!16758> (cherry picked from commit 4b5bb213)
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this is not a requirement for any version of GL, so don't pretend it's a requirement cc: mesa-stable Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!16758> (cherry picked from commit 63a9e0a9)
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These were spilled unconditionally. Cc: mesa-stable Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <mesa/mesa!16708> (cherry picked from commit 8e41c666)
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Fixes: 721b880e ("script: drop get_reviewer.pl") Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!16786> (cherry picked from commit 61a50349)
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Fixes: 95aefc94 ("Delete autotools") Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!16786> (cherry picked from commit 799bf3d6)
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Fixes: 44a4e34d ("docs: remove doxygen support") Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!16786> (cherry picked from commit 12aa3b82)
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Fixes: 6e6cd7d9 ("scons: Remove.") Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <!16786> (cherry picked from commit 7a088d35)
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cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!16776> (cherry picked from commit 9f702916)
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Fixes: 34b3b92b ("nir/xfb: move varyings info out of nir_xfb_info") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!16750> (cherry picked from commit 36d8a2f1)
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this avoids looking at irrelevant 3d pixelstore params like GL_PACK_IMAGE_HEIGHT when they don't apply, which will cause the storage buffer to be incorrectly sized and break the operation Fixes: e7b95619 ("gallium: implement compute pbo download") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!16728> (cherry picked from commit 70fb3a47)
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cc: mesa-stable Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <!16757> (cherry picked from commit aaf0d449)
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cc: mesa-stable Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <mesa/mesa!16757> (cherry picked from commit 591da8cf)
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During certain control-flow manipulation passes, we go out-of-SSA temporarily in certain areas of the code to make control-flow manipulation easier. This can result in registers being in phi sources temporarily. If two sub-passes run before we get a chance to do clean-up, we can end up doing some out-of-SSA and then a bit more out-of-SSA and trigger this case. It's easy enough to handle. Fixes: a620f668 ("nir: Add a couple quick-and-dirty out-of-SSA helpers") Fixes: 79a987ad ("nir/opt_if: also merge break statements with ones after the branch") Closes: mesa/mesa#6370 Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!16111> (cherry picked from commit 4a4d6cdc)
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sparc.h was removed in when the classic drivers were removed. It only contained a prototype for _mesa_init_all_sparc_transform_asm() which wasn't even called by context.c. Remove the #include to fix the build on sparc. Fixes: e030d5ba ("mesa: Delete libmesa_classic") Closes: mesa/mesa#6425 Part-of: <mesa/mesa!16765> (cherry picked from commit 27f3fb56)
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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Fixes: 58bd9a37 ("aco/ra: fix live-range splits of phi definitions") Part-of: <mesa/mesa!16454> (cherry picked from commit cd2b4c31)
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VkAccelerationStructureBuildRangeInfoKHR spec: If the geometry uses indices, primitiveCount × 3 indices are consumed from VkAccelerationStructureGeometryTrianglesDataKHR::indexData, starting at an offset of primitiveOffset. The value of firstVertex is added to the index values before fetching vertices. If the geometry does not use indices, primitiveCount × 3 vertices are consumed from VkAccelerationStructureGeometryTrianglesDataKHR::vertexData, starting at an offset of primitiveOffset + VkAccelerationStructureGeometryTrianglesDataKHR::vertexStride × firstVertex. Meaning: We always add firstVertex * vertexStride to the vertex address and add primitiveOffset either to the vertex address or the index address, depending on wether indices are used. Also add missing handling with instances. Fixes: 0dad88b4 ("radv: Implement device-side BVH building.") Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!16719> (cherry picked from commit 9be00573) Conflicts: src/amd/vulkan/radv_acceleration_structure.c
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It turns out that we need a fragment shader for streamout. Whh? From Lionel's reading of simulator sources, it seems the streamout unit is looking at enabled next stages. It'll generate output to the clipper in the following cases : - 3DSTATE_STREAMOUT::ForceRendering = ON - PS enabled - Stencil test enabled - depth test enabled - depth write enabled - some other depth/hiz clear condition Forcing rendering without a PS seems like a recipe for hangs so it's probably better to just enable the PS in this case. Fixes: 36ee2fd6 ("anv: Implement the basic form of VK_EXT_transform_feedback") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!16506> (cherry picked from commit 0d28de21)
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Actually compile and cache the no-op fragment shader but remove it from the pipeline if we determine it's a no-op. This way we always have it even if it's not strictly needed. Fixes: 36ee2fd6 ("anv: Implement the basic form of VK_EXT_transform_feedback") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!16506> (cherry picked from commit 73b3efcd)
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Starting with Ivy Bridge, we implement alpha-to-coverage by writting gl_SampleMask with a pattern based on alpha. This will show up in wm_prog_data::uses_omask so we don't need to look at the key. Fixes: 36ee2fd6 ("anv: Implement the basic form of VK_EXT_transform_feedback") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!16506> (cherry picked from commit 9fe6caf4)
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Fixes: 36ee2fd6 ("anv: Implement the basic form of VK_EXT_transform_feedback") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!16506> (cherry picked from commit 1b9248e7)
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In wsi_destroy_image(), if buffer_blit_queue then do not call extra free. This will fix assert in debug release and accessing out of allocated memory. Fixes: 7bd5aa11 ("vulkan/wsi: add a private transfer pool to exec the DRI_PRIME blit") Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!16649> (cherry picked from commit 1a8b0373)
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Fixes: 4bb45bcd ("zink: add error logging for SRGB framebuffer without KHR_swapchain_mutable_format") Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <!16642> (cherry picked from commit c97aee42) Conflicts: src/gallium/drivers/zink/zink_context.c
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Dylan Baker authored
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these are different renderpasses according to compatibility rules cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!16621> (cherry picked from commit 8fef8ed1)
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improve compatibility detection cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!16621> (cherry picked from commit f4aa727e)
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Found by insepction. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!16698> (cherry picked from commit 1046c2a1)
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The kms_swrast path calls this callback via the dri2 paths, not flushing caused artifacts when running inside a VM or on hw in weston/gnome-shell. Fixes: 6bbbe15a ("Reinstate: llvmpipe: allow vertex processing and fragment processing in parallel") Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!16715> (cherry picked from commit c219ca3f)
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According to the Vulkan spec 21.4 "Conditional Rendering", only clearing attachments with vkCmdClearAttachments is subject to conditional rendering. Subpass clear and vkCmdClearColorImage / vkCmdClearDepthStencilImage should always be executed even if it happens in a conditional rendering block. Cc: mesa-stable Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!16654> (cherry picked from commit 55466ca5)
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We don't want to modify sel->nir so force the use of the serialized version of the shader. Waiting on sel->ready guarantees that sel->nir will be NULL and that si_get_nir_shader will use sel->nir_binary. Fixes: b78a38bd ("radeonsi: use si_nir_is_output_const_if_tex_is_const") Closes: mesa/mesa#6415 Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!16587> (cherry picked from commit ef950d37)
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MEC (the compute queue firmware) does not support real predication, so we have to emulate that using COND_EXEC packets before each dispatch. Additionally, COND_EXEC doesn't have an inverted mode, so in order to support inverted mode conditional rendering, we allocate a new piece of memory in which we invert the condition. Cc: mesa-stable Closes: #6533 Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!16653> (cherry picked from commit 85a4c5b3)
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When vulkan enables depth bias, enable it for all 3 prim types in gallium. This fixes: dEQP-VK.draw.renderpass.depth_bias.depth_bias_* and one zink test in CI Cc: mesa-stable Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!16701> (cherry picked from commit 4896e136)
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This commit increases the maximum line width to 8.0 for SLK+ and to 7.9921875 for BDW and earlier. Closes: mesa/mesa#6234 Fixes: fce0027d ("anv: Unbreak wide lines on HSW/BDW") Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!15879> (cherry picked from commit 10b6d923)
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We can't assume that RT0 will be written, so this has to be based on whether a combined store has already been emitted, not the location of the store. Emit a non-special combined_store intrinsic that only writes colour for the other RTs, as reordering stores breaks the Midgard compiler. Fixes: d37e901e ("pan/mdg: Add new depth store lowering") Closes: #6527 Part-of: <!16685> (cherry picked from commit a4323b09)
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Fixes depth/stencil writes with MRT. Fixes: b3d72727 ("pan/mdg: Don't read base for combined stores") Part-of: <mesa/mesa!16685> (cherry picked from commit 0a53ebab)
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It's meaningful for this intrinsic and so does not add noise to the lowering pass. (Although dual-source writes must be to RT 0, depth and stencil writes, which store_combined_output_pan is also used for, can still be done with MRT enabled.) Fixes: 5c168f09 ("nir: Eliminate store_combined_output_pan BASE") Part-of: <mesa/mesa!16685> (cherry picked from commit 9f9ed959)
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Dylan Baker authored
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