- Dec 07, 2023
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José Roberto de Souza authored
Iris and KMD needs to be able to read and write the clear-color from CPU. So here it make sure that bos with the clear color information are placed in a lmem portion that is CPU-visible, that is important in PCIe small bar systems. And as CCS in discrete GPUs are only supported in lmem this bo can't become a IRIS_HEAP_DEVICE_LOCAL_PREFERRED(lmem + smem). So here the IRIS_HEAP_DEVICE_LOCAL_CPU_VISIBLE heap is selected. This issue was happening in i915 and Xe KMD as for both clear_color_unknown is set to true in iris_resource_init_aux_buf() but this worst in Xe KMD as it rejects the page flips if it can't read the clear-color from CPU. Signed-off-by:
José Roberto de Souza <jose.souza@intel.com>
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José Roberto de Souza authored
This is intented to be used in cases where BOs can only be placed in lmem but needs to accesible from CPU side. Actual usage will be added in the next patch, here just adding the heap type and all the handling. Signed-off-by:
José Roberto de Souza <jose.souza@intel.com>
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José Roberto de Souza authored
Information in iris_resource will be needed so here replacing isl_aux_usage by iris_resource. Signed-off-by:
José Roberto de Souza <jose.souza@intel.com>
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José Roberto de Souza authored
iris_get_aux_clear_color_state_size() will be called from iris_resource_alloc_flags() in a future patch, so moving it here to make future patch cleaner. Signed-off-by:
José Roberto de Souza <jose.souza@intel.com>
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José Roberto de Souza authored
squash
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José Roberto de Souza authored
i915 and Xe KMD uAPIs don't return the available sram and lmem available for applications without CAP_PERFMON or CAP_SYS_ADMIN privileges, so here lets do what i915 does and query the available smem from sysfs. Signed-off-by:
José Roberto de Souza <jose.souza@intel.com>
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Requirement was lowered in the extension spec: https://github.com/KhronosGroup/OpenGL-Registry/pull/596 Signed-off-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!26500>
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Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Acked-by:
Eric Engestrom <eric@igalia.com> Part-of: <mesa/mesa!26515>
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Make them generated in consistent way Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Acked-by:
Eric Engestrom <eric@igalia.com> Part-of: <mesa/mesa!26515>
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Make them generated in consistent way Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Acked-by:
Eric Engestrom <eric@igalia.com> Part-of: <!26515>
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This is for fixes the following error: FAILED: src/vulkan/runtime/vk_synchronization_helpers.c src/vulkan/runtime/vk_synchronization_helpers.h "C:\CI-Tools\msys64\mingw64\bin/python3.EXE" "../../src/vulkan/util/vk_synchronization_helpers_gen.py" "--xml" "../../src/vulkan/registry/vk.xml" "--out-c" "src/vulkan/runtime/vk_synchronization_helpers.c" "--beta" "false" Traceback (most recent call last): File "C:/work/xemu/mesa/src/vulkan/util/vk_synchronization_helpers_gen.py", line 213, in main f.write(TEMPLATE_C.render(**environment)) UnicodeEncodeError: 'gbk' codec can't encode character '\xa9' in position 15: illegal multibyte sequence Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Acked-by:
Eric Engestrom <eric@igalia.com> Part-of: <mesa/mesa!26515>
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Closes: mesa/mesa#10234 Part-of: <mesa/mesa!26464>
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For working around improper usage of sparse in DOOM Eternal. When fully explicit sync sparse binding is implemented, this path will remain implicit sync to also deal with the improper semaphore usage. radv_queue_submit_bind_sparse_memory will likely get a bool parameter to control explicit / implicit sync in that case. Part-of: <mesa/mesa!26464>
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Part-of: <mesa/mesa!26406>
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Part-of: <mesa/mesa!26279>
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Part-of: <mesa/mesa!26279>
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Part-of: <mesa/mesa!26279>
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Part-of: <mesa/mesa!26279>
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Part-of: <mesa/mesa!26279>
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Part-of: <mesa/mesa!26279>
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Part-of: <mesa/mesa!26280>
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Part-of: <mesa/mesa!26280>
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Part-of: <mesa/mesa!26257>
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Part-of: <mesa/mesa!26257>
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This commit replace the CPU-conversion of ubyte to ushort by a compute shader. The benefits are: * we don't need to sync anymore * we can allocate the index buffer in VRAM (no need to CPU map it) Closes: mesa/mesa#10195 Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!26416>
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Part-of: <mesa/mesa!26258>
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Part-of: <mesa/mesa!26258>
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Part-of: <mesa/mesa!26258>
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Part-of: <mesa/mesa!26258>
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Fixes: 70eff587 ("ci: allow hw jobs even if lint jobs fail for non-Marge pipelines") Part-of: <mesa/mesa!26511>
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This is now done in the NIR linker instead. Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!26534>
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Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!26534>
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This added support for names and some extra validation that the spirv linker does not require. Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!26534>
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This will be used to fix up types after arrays have been resized. Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!26534>
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align is a function and when we want use it, the align variable will shadow it So replace it with other names Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <!25997>
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align is a global function, do not conflict with it Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <mesa/mesa!25997>
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Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <mesa/mesa!25997>
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The libraries that use OpenGL already handling the non-exist of OpenGL headers for both MSVC and MINGW, so there is no need install them Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Acked-by:
Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!14019>
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The warp barriers go back to SM70, not SM75. Part-of: <mesa/mesa!26114>
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Part-of: <mesa/mesa!26114>
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