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Commit 603791bd authored by Connor Abbott's avatar Connor Abbott Committed by Marge Bot
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ir3: Bump type mismatch penalty to 3

After some experimentation with computerator, it seems on a618 that
writing a full register and then reading half of it as a half register
requires a delay of 6, the same as the delay for cat5/cat6 sources. The
other direction only has a delay of 5, but just bump it unconditionally
out of an abundance of caution.

Fixes: 890de1a4 ("ir3/delay: Fix full->half and half->full delay")
Part-of: <mesa/mesa!14246>
parent d371d807
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