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Commit 890de1a4 authored by Connor Abbott's avatar Connor Abbott Committed by Emma Anholt
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ir3/delay: Fix full->half and half->full delay

The current compiler never does this, but the new compiler will start to
in mergeregs mode. There is an extra penalty for this.

Part-of: <mesa/mesa!9842>
parent 9ad83f51
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......@@ -88,12 +88,25 @@ ir3_delayslots(struct ir3_instruction *assigner,
if (is_flow(consumer) || is_sfu(consumer) || is_tex(consumer) ||
is_mem(consumer)) {
return 6;
} else if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) &&
(n == 3)) {
/* special case, 3rd src to cat3 not required on first cycle */
return 1;
} else {
return 3;
/* assigner and consumer are both alu */
assert(n > 0);
/* In mergedregs mode, there is an extra 2-cycle penalty when half of
* a full-reg is read as a half-reg or when a half-reg is read as a
* full-reg.
*/
bool mismatched_half =
(assigner->regs[0]->flags & IR3_REG_HALF) !=
(consumer->regs[n - 1]->flags & IR3_REG_HALF);
unsigned penalty = mismatched_half ? 2 : 0;
if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) &&
(n == 3)) {
/* special case, 3rd src to cat3 not required on first cycle */
return 1 + penalty;
} else {
return 3 + penalty;
}
}
}
......
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