- May 05, 2021
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Eric Engestrom authored
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Eric Engestrom authored
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- May 04, 2021
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cores_per_L3 was uninitialized, so it was always disabled. Remove the variable and do it differently. Fixes: 11d2db17 - util: rework AMD cpu L3 cache affinity code. Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!10526> (cherry picked from commit 48d2ac4e)
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There's a recently discovered HW bug affecting hardware at least as far back as Skylake where, if the LOD is out-of-bounds for any SIMD lane, then garbage may be returned in all SIMD lanes. The easy solution is to set lower_txs_lod so that we always have a constant LOD of 0 which we know a priori is always in-bounds. Fortunately, not many shaders actually use textureSize() with LOD. Shader-db results on Ice Lake: total instructions in shared programs: 19948537 -> 19948564 (<.01%) instructions in affected programs: 3859 -> 3886 (0.70%) helped: 0 HURT: 7 One of the shaders is in Civilization: Beyond Earth, and the rest are all in Civilization VI. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Cc: mesa-stable@lists.freedesktop.org Part-of: <mesa/mesa!10538> (cherry picked from commit 05a37e24)
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a0.x is written as a half-reg, but just interpreting it as "hr61.x" will result in it overlapping with r30.z in merged mode, which is not what the hardware does at all. This introduced a spurious dependency on a write to r30.z which resulted in an assert tripping. Just pretend it's a full reg instead. This fixes spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs with the new RA. Fixes: 0f78c324 ("freedreno/ir3: post-RA sched pass") Part-of: <mesa/mesa!10591> (cherry picked from commit e597f8b1)
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Eric Engestrom authored
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- May 03, 2021
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This reverts f0861c80 which causes regression on multiple apps that require a sRGB capable visual. Closes: mesa/mesa#4690 Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <mesa/mesa!10498> (cherry picked from commit fc408549)
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RADV doesn't try to keep anything 16 or 32 byte aligned. RADV also seems to create better code for some reason. fossil-db (Sienna Cichlid): Totals from 37693 (30.93% of 121873) affected shaders: SGPRs: 1762792 -> 1785504 (+1.29%); split: -1.01%, +2.30% VGPRs: 1761032 -> 1760808 (-0.01%); split: -0.09%, +0.07% SpillSGPRs: 55793 -> 56011 (+0.39%); split: -3.49%, +3.88% SpillVGPRs: 16766 -> 16387 (-2.26%); split: -3.99%, +1.73% CodeSize: 82902228 -> 82781608 (-0.15%); split: -0.29%, +0.14% Scratch: 3024896 -> 2987008 (-1.25%); split: -3.08%, +1.83% MaxWaves: 919794 -> 920302 (+0.06%); split: +0.09%, -0.03% shader-db (Sienna Cichlid): Totals from affected shaders: SGPRS: 3976 -> 3976 (0.00 %) VGPRS: 3392 -> 3392 (0.00 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 178792 -> 178980 (0.11 %) bytes Max Waves: 1389 -> 1389 (0.00 %) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Cc: mesa-stable Closes: mesa/mesa#4715 Part-of: <mesa/mesa!10543> (cherry picked from commit d918a59d)
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Based on the previous commit. Fixes: 012773be ("turnip: Configure VPC for geometry shaders") Part-of: <mesa/mesa!10551> (cherry picked from commit 3d5c1c49)
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Turns out kernel 4.15 only goes up to amdgpu 3.23 . 3.35 is way too new. Too new for e.g. ChromeOS. Fixes: 1df4f11e ("radv: require DRM 3.35+") Closes: mesa/mesa#4728 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!10576> (cherry picked from commit edc600d0)
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If the secondary has a list of CS buffers, it should be copied to the primary. Fixes dEQP-VK.api.command_buffers.record_many_draws_secondary_2. Cc: 21.1 mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!10547> (cherry picked from commit 12a00da8)
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The "continue" was placed in the wrong loop, leading to exec being counted as a spilled register when it wasn't. Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Fixes: a56ddca4 ('aco: make all exec accesses non-temporaries') Closes: mesa/mesa#4533 Part-of: <mesa/mesa!10486> (cherry picked from commit 741e84f5)
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Fixes an assertion triggered by new CTS: dEQP-VK.renderpass2.suballocation.multisample_resolve.*_resolve_level_* Looks like the driver should pass a range to radv_layout_dcc_compressed(). Cc: 21.1 mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!10502> (cherry picked from commit 80f55e51)
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Users have reported a rise in trust factor problems [1] since using mesa builds containing 6f201720. Until we confirm its not a problem disable glthread. [1] https://github.com/ValveSoftware/csgo-osx-linux/issues/2630 Fixes: 6f201720 ("dri: enable glthread + radeonsi workaround for CS:GO") Closes: mesa/mesa#4710 Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!10540> (cherry picked from commit 40c93e2f)
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Eric Engestrom authored
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- May 02, 2021
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Since commit f39fd3dc a new GLX error is issued in case context creation fails. This broke wine on certain hardware: While wine installs an error handler to ignore this kind of error, it does not function because it expects the dpy->request serial number of the error to be incremented since the installation of the handler. Workaround this by artificially increasing the request number. This also guarantees a unique serial number for the error. Fixes: f39fd3dc Closes: mesa/mesa#3969 Signed-off-by: Bastian Beranek <bastian.beischer@rwth-aachen.de> Part-of: <mesa/mesa!10565> (cherry picked from commit 960c86d6)
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The max values are inclusive, so add 1 before aligning. This means that a max of 32 will be aligned up to 64 then be decremented to 63. Add a comment to the pan_fb_info struct to document maxx and maxy as inclusive. Fixes: 8ba2f9f6 ("panfrost: Create a blitter library to replace the existing preload helpers") Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!10542> (cherry picked from commit ab8e531c)
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Eric Engestrom authored
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- Apr 30, 2021
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The prototype uses a pointer and the actual function definition had an array. For some reason, GCC never complained about this until GCC 11. This fixes a compile warning when building with GCC 11. Fixes: 09ced654 "intel/isl: Add format conversion code" Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!10537> (cherry picked from commit b80720ac)
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Make the rmu variable signed; otherwise the MAX2 has no effect and work_count can end up being larger than 16. Fixes INSTR_OPERAND_FAULTs in SuperTuxKart. Closes: mesa/mesa#4707 Fixes: c6ed8bf7 ("panfrost: Fix uniform_count on Midgard") Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!10507> (cherry picked from commit f85b7aa5)
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With the missing else, this prints the compacted hex followed by hex for an uncompacted version of the compacted instruction. It also doesn't print hex for instructions that are not compacted. Fixes: bc4a127d ("intel/disasm: Label support in shader disassembly for UIP/JIP") Fixes: mesa/mesa!4245 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <mesa/mesa!10535> (cherry picked from commit 3f043835)
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We were exposing as available DRM_FORMAT_MOD_BROADCOM_SAND128 for any format. Fixes: 95c4f0f9 "v3d: Enables DRM_FORMAT_MOD_BROADCOM_SAND128 support" Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!10524> (cherry picked from commit 5a503727)
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This fixes Issue https://github.com/Igalia/meta-webkit/issues/185 "Issue Raspberry 4-64 + Mesa VC4 driver + Gstreamer = red Label on video" Fixes: 95c4f0f9 "v3d: Enables DRM_FORMAT_MOD_BROADCOM_SAND128 support" Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!10524> (cherry picked from commit 9094ad7c)
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This fixes Issue https://github.com/Igalia/meta-webkit/issues/185 "Issue Raspberry 4-64 + Mesa VC4 driver + Gstreamer = red Label on video" Fixes: 6ee10ab3 "gallium: Add pipe_screen::is_dmabuf_modifier_supported" Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!10524> (cherry picked from commit 3d7b3789)
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Dylan Baker authored
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- Apr 29, 2021
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For non 64bit devices the key stored in hash_table_u64 is wrapped in hash_key_u64 structure, which is never free. This commit fixes this issue by just removing the user-defined `delete_function` parameter in hash_table_u64_{destroy,clear} (which nobody is using) and using instead a delete function to free this structure. Fixes: 608257cf ("i965: Fix INTEL_DEBUG=bat") Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Part-of: <mesa/mesa!10480> (cherry picked from commit e532a47f) Conflicts: src/microsoft/compiler/dxil_nir.c
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If radv_pipeline_cache_insert_shaders() finds a GS copy shader in the cache, it will free the variant in gs_variants and replace it with the one in the cache. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Cc: mesa-stable Part-of: <mesa/mesa!10433> (cherry picked from commit d6894b64)
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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Fixes: bd1705a4 ("vulkan: Make vk_debug_report_callback derive from vk_object_base") Part-of: <mesa/mesa!10433> (cherry picked from commit 32ebbd8c)
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The NGG GS state uses one user SGPR. Cc: 21.1 mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <mesa/mesa!10485> (cherry picked from commit c425b67c)
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The game has a shader that uses texture functions that rely on implicit derivatives after a discard. Cc: mesa-stable Closes: mesa/mesa#4547 Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!10278> (cherry picked from commit 0477fbc6)
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Dylan Baker authored
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- Apr 28, 2021
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The idea behind this assert is that if a buffer is in bufmgr->handle_table it's because it has been shared from i965 to the outside. This is when we add the drm FD associated to this BO to bo->exports. But we also import buffer from the outside into i965 and those buffers don't have an associated drm FD added to bo->exports. If you import the same buffer more than once, you'll run into this assert. v2: Also drop assert from brw_bo_gem_create_from_name() (Ian) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 57e4d0aa ("i965: fix export of GEM handles") Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!10386> (cherry picked from commit 03e97e94)
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This partially deals with mesa/mesa#4688 Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <mesa/mesa!10430> (cherry picked from commit 6b61fbca)
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Dylan Baker authored
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Dylan Baker authored
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- Apr 27, 2021
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I mixed up the EXT and ARB version of the extensions; we actually do require shaderStorageImageWriteWithoutFormat as well here. Thanks to Ilia Mirkin for pointing this out. It also seems I got really confused about what was required when writing the docs, so let's fix that as well. Fixes: 341332b2 ("zink: correct image cap checks") Fixes: ecac7f3d ("docs: add missing zink-requirement") Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <mesa/mesa!10463> (cherry picked from commit 4ec8533f) Conflicts: docs/drivers/zink.rst
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This fixes a bunch of MSAA related CTS regressions. This restores previous behaviour on GFX9 but it should be fixed properly. Cc: 21.1 mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!10374> (cherry picked from commit a854a9fa)
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because different DCC equations are used. Fixes: 3120113e - radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9 Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!10343> (cherry picked from commit 1f8fa964)
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$(MESA_TOP)/src/compiler/nir include path is added for both clarity and build errors preventive reasons Cc: 21.0 21.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!10443> (cherry picked from commit a0232839)
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Since generated nir headers are included, it makes sense to include nir path Fixes the following building error: FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/si_shader_nir.o ... In file included from external/mesa/src/gallium/drivers/radeonsi/si_shader_nir.c:26: external/mesa/src/amd/common/ac_nir.h:29:10: fatal error: 'nir.h' file not found ^~~~~~~ 1 error generated. Cc: 21.0 21.1 <mesa-stable@lists.freedesktop.org> Fixes: 1c702a82 ("ac: move ac_lower_indirect_derefs() outside of the LLVM dir") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!10443> (cherry picked from commit e213bfd3)
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