Skip to content
GitLab
Explore
Sign in
Register
Mesa
mesa
Merge requests
Open
15
Merged
314
Closed
32
All
361
Actions
Subscribe to RSS feed
Recent searches
{{formattedKey}}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Created date
freedreno/ir3: Enable core NIR's 16-bit ALU optimizations.
!17546
· created
Jul 14, 2022
by
Emma Anholt
ir3
turnip
Merged
8
updated
Jul 18, 2022
ir3: Fix the no-emitted-vertex condition emission in geom lowering.
!17501
· created
Jul 12, 2022
by
Emma Anholt
ir3
Merged
3
updated
Jul 27, 2022
nir: SSBO array length fixes and optimizations.
!17468
· created
Jul 11, 2022
by
Georg Lehmann
NIR
TGSI
ir3
r600
zink
Merged
8
updated
Jul 19, 2022
Fix skqp GS hangs and GS clip-plane
!17341
· created
Jul 01, 2022
by
Rob Clark
freedreno
ir3
Merged
6
updated
Jul 27, 2022
ir3: Fix interpolateAtOffset() for different interpolation modes
!17322
· created
Jun 30, 2022
by
Emma Anholt
ir3
turnip
Merged
16
updated
Jul 11, 2022
ir3: Retire the cp postsched pass now that we do RA in SSA.
!17320
· created
Jun 30, 2022
by
Emma Anholt
ir3
Merged
2
updated
Jul 04, 2022
freedreno: parallel_shader_compile stuff
!17124
· created
Jun 19, 2022
by
Christian Gmeiner
freedreno
ir3
Merged
1
updated
Jun 22, 2022
ir3: Fix vectorizer condition for SSBOs
!17040
· created
Jun 14, 2022
by
Connor Abbott
ir3
turnip
Merged
3
updated
Jun 23, 2022
nir: Rewrite and merge 16bit tex folding pass with 16bit image folding pass.
!16978
· created
Jun 10, 2022
by
Georg Lehmann
NIR
ir3
Merged
46
updated
Jul 21, 2022
ir3: Use NIR's info.writes_memory to detect when when to force late-z
!16818
· created
Jun 01, 2022
by
Danylo Piliaiev
ir3
Merged
3
updated
Jul 01, 2022
ir3: Force late-z if FS has global store/atomic
!16816
· created
Jun 01, 2022
by
Danylo Piliaiev
ir3
Merged
3
updated
Jun 01, 2022
ir3: handle intrinsic_load_draw_id when scanning driver constants
!16769
· created
May 30, 2022
by
Hyunjun Ko
ir3
turnip
Merged
1
updated
May 31, 2022
ir3: handle gl_Layer and gl_ViewportIndex when there is TES + GS
!16696
· created
May 24, 2022
by
Danylo Piliaiev
ir3
Merged
4
updated
May 26, 2022
ir3/sched: Fix could_sched() determination
!16635
· created
May 20, 2022
by
Connor Abbott
ir3
Merged
4
updated
Jun 22, 2022
freedreno: Lower mediump sampler coordinates and image load/store, vectorize SSBOs.
!16616
· created
May 19, 2022
by
Emma Anholt
NIR
ir3
performance
Merged
7
updated
Jun 01, 2022
spirv,turnip: Use 16 bit for RelaxedPrecision-decorated ALU ops
!16465
· created
May 12, 2022
by
Emma Anholt
SPIR-V
ir3
turnip
Merged
17
updated
Nov 21, 2023
nir/lower_blend: Misc fixes
!16309
· created
May 03, 2022
by
Faith Ekstrand
NIR
RADV
SPIR-V
asahi
blorp
ir3
panfrost
panvk
Merged
27
updated
Jun 01, 2022
turnip: "Real" pipeline cache using the shared Vulkan cache
!16147
· created
Apr 25, 2022
by
Connor Abbott
freedreno
ir3
turnip
Merged
13
updated
May 20, 2022
turnip,ir3: debug and opts for vulkan gfxbench
!15982
· created
Apr 15, 2022
by
Emma Anholt
ir3
performance
turnip
Merged
8
updated
Apr 19, 2022
freedreno/a6xx: Add EARLYPREAMBLE flag to all a6xx_sp_xs_ctrl_reg0
!15901
· created
Apr 12, 2022
by
Danylo Piliaiev
freedreno
ir3
Merged
6
updated
May 18, 2022
Prev
1
2
3
4
5
6
7
8
9
10
…
16
Next