- May 25, 2023
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Eric Engestrom authored
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Eric Engestrom authored
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If two threads deserialize the raw object at the same time, the refcount could be more than 1 temporarily. This can be reproduced with Granite during the multi-threaded pipeline cache pre-warm on startup, and also with Dota2. Fixes: cbab396f ("vulkan/pipeline_cache: replace raw data objects on cache insertion of real objects") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <!22853> (cherry picked from commit 8126e028)
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 415b824b ("iris: implement occlusion query related Wa_14017076903") Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <!22807> (cherry picked from commit 1d13f221)
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This should be set to the enum, ffmpeg has it wrong so far, but the sample decoder has it right. convert radv to the proper answer. Fixes: 1693c03a ("radv/video: add initial h264 decoder for VCN") Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!23225> (cherry picked from commit ea2eade5)
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I'm sure this was broken. Fixes: 1bf39b1f - ac,radeonsi: rework how scratch_waves is used and move it to ac_gpu_info.c Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <!23221> (cherry picked from commit 474f9fbe)
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Fixes: 96913bbf - ac/surface: force linear image layout for chips not supporting image opcodes Closes: #9073 Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <!23221> (cherry picked from commit fe03351b)
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Fixes: 68a926a1 ("glthread: set GL_OUT_OF_MEMORY if we fail to upload vertices") Signed-off-by: Patrick Lerda <patrick9876@free.fr> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <!23166> (cherry picked from commit 39a9ebde)
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Fixes: 03ba57c6 - mesa: extend _mesa_bind_vertex_buffer to take ownership of the buffer reference Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Part-of: <!23112> (cherry picked from commit ce3edf51)
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Indeed, the locally allocated "stimg" reference was not freed on a specific code path. For instance, this issue is triggered on radeonsi or r600 with: "piglit/bin/egl-ext_egl_image_storage -auto -fbo" while setting GALLIUM_REFCNT_LOG=refcnt.log. Fixes: 6a3f5c65 ("mesa: simplify st_egl_image binding process for texture storage") Signed-off-by: Patrick Lerda <patrick9876@free.fr> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <!23165> (cherry picked from commit 83cd7d23)
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When the fragment shader reads the VRS builtin, VRS flat shading shouldn't be enabled, otherwise the value might not be what the FS expects. Fixes dEQP-VK.fragment_shading_rate.renderpass2.monolithic.multipass.* on RDNA2 (VRS flat shading isn't yet enabled on RDNA3). Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <!23187> (cherry picked from commit b439bd5a)
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fixes: 7c41cdb8 Reviewed-by: Qiang Yu <yuq825@gmail.com> Part-of: <!23178> (cherry picked from commit e3676176)
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use update_decoder_target to update the target buffer to let decoder obtain correct reference frame. remove the previous logic which failed to update reference info in time. fixes: #8996 fixes: #8387 Cc: mesa-stable Reviewed-by: Sil Vilerino <sivileri@microsoft.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <!23061> (cherry picked from commit 799665c9)
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implement update_decoder_target and remove corresponding obsolete logic. Cc: mesa-stable Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <!23061> (cherry picked from commit a89f740e)
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reason: decoder uses the target buffer address in record to indentify the reference frames. When target buffer has changed outside of decoding process, it has to be updated back to decoder, otherwise the outdated reference will cause image corruption. Cc: mesa-stable Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Reviewed-by: Sil Vilerino <sivileri@microsoft.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <!23061> (cherry picked from commit 5b2544f8)
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Eric Engestrom authored
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The query result resource will be written to by the host, so we have to declare it as dirty if we want to see the change. Fixes: 9279a28f (virgl: ARB_query_buffer_object support) v2: Update expectations in CI Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <mesa/mesa!23121> (cherry picked from commit 330a1db0)
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With Anv/Zink, the piglit test : arb_shader_storage_buffer_object-max-ssbo-size -auto -fbo fsexceed is failing validation after copy propagation : load_payload(8) vgrf15:F, vgrf1+0.12<0>:F, vgrf1+0.0<0>:F, vgrf1+0.4<0>:F, vgrf1+0.8<0>:F, vgrf1+0.12<0>:F ../src/intel/compiler/brw_fs_validate.cpp:191: A <= B failed A = inst->src[i].offset / REG_SIZE + regs_read(inst, i) = 2 B = alloc.sizes[inst->src[i].nr] = 1 In most cases it works because src[0] would be at offset 0 and so reading a full reg passes validation, but Anv/Zink started emitting slightly different code adding an offset maybe the size read 2 GRFs. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Cc: mesa-stable Part-of: <mesa/mesa!23126> (cherry picked from commit 21c7b55f)
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Found by manual inspection. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Fixes: 7acc8105 ("compiler/nir: Add support for variable initialization from a pointer") Part-of: <mesa/mesa!22355> (cherry picked from commit 1546a9de)
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Fixes: 854fd242 ("zink: declare int/float size caps inline with type usage") Part-of: <mesa/mesa!22934> (cherry picked from commit 5d8103b1)
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has_work controls whether a flush can be deferred, i.e., when unset a flush may be deferred since a promoted cmd must still be flushed to take effect, ensure this is always set when promoted cmds are pending cc: mesa-stable Part-of: <mesa/mesa!23035> (cherry picked from commit 0f510040)
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when needs_present_readback is set, reordering is disabled without hitting the path that would normally disable promotion for the resource, so this needs to be changed manually to avoid layout desync on the swapchain cc: mesa-stable Part-of: <mesa/mesa!23035> (cherry picked from commit 3c010319)
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this is consistent with other cmdbuf reordering for blits Fixes: 3a9f7d70 ("zink: implement unordered u_blitter calls") Part-of: <mesa/mesa!23035> (cherry picked from commit ab3914a1)
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in a scenario where an ordered read op occurs for an image, successive read-only barriers SHOULD be able to be promoted ...but they can't, because there isn't yet a mechanism for handling layout transitions between the unordered cmdbuf and the ordered cmdbuf, meaning that promoting e.g., a SHADER_READ_ONLY barrier after a TRANSFER_SRC barrier will leave the image with the wrong layout for the transfer op: TRANSFER_SRC(unordered) -> COPY(ordered) -> SHADER_READ_ONLY(unordered) becomes TRANSFER_SRC(unordered) -> SHADER_READ_ONLY(unordered) -> COPY(ordered) ideally I'll get around to figuring this out at some point affects: dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.r32i_r32i.texture2d_array_to_renderbuffer Fixes: bf0af0f8 ("zink: move all barrier-related functions to c++") Part-of: <mesa/mesa!23035> (cherry picked from commit 9c8b6754)
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in the case where a draw is triggered after a flush, zink_update_descriptor_refs will be called to set batch tracking for descriptors. this function also handles refs for fb attachments, and everything is usually fine there the problem with this approach is that tracking is no longer set on view objects at renderpass begin, which makes them susceptible to early deletion if a rp isn't started from a draw call instead, apply batch tracking to fb attachment resources on renderpass begin if the BATCH_CHANGED flag is set (need to rename this at some point) in order to guarantee that the resource (object) lifetime will match the cmdbuf runtime [since imageviews are now only freed upon batch completion] fixes #9059 Fixes: f6bbd787 ("zink: remove batch tracking/usage from view types" Part-of: <mesa/mesa!23132> (cherry picked from commit 62961b17)
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Yuzu is running into a segfault because it writes the push descriptor twice with 2 different layouts, but without a draw/dispatch in between. First vkCmdPushDescriptorSetKHR() writes descriptor 0 & 1 with a uniform buffer. We toggle the 2 first bits of anv_descriptor_set::generate_surface_states. Second vkCmdPushDescriptorSetKHR() writes descriptor 0 with uniform buffer and descriptor 1 with an image view. The first bit of anv_descriptor_set::generate_surface_states stays, but the second bit was already set before and it should now be off. When we finally flush the push descriptor, we try to generate a surface state for descriptor 1, but there is no valid buffer view for it, we access an invalid pointer and segfault. This fix resets the anv_descriptor_set::generate_surface_states when the descriptor layout changes. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: b49b18f0 ("anv: reduce BT emissions & surface state writes with push descriptors") Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!23156> (cherry picked from commit cab7ba00)
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-1 is a legit vertex offset upon vkCmdDrawIndexed and other cmds. This change fixes to track last_vertex_offset with an additional valid bit. Cc: mesa-stable Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org> Part-of: <mesa/mesa!23157> (cherry picked from commit 4c8be22c)
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This shouldn't have been enabled at all. Depth-stencil formats were accidentally disabled but not depth-only or stencil-only formats. This doesn't seem allowed by DX12 and both AMD/NVIDIA don't enable it. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!23122> (cherry picked from commit dda7400c)
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Super sampling on a 4K screen could hit this. 16k seems pretty big but this image is only created on RDNA2 and on-demand if VRS attachments are used without depth-stencil attachments, which should be rare enough to care. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!23105> (cherry picked from commit 3adc9b67)
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Eric Engestrom authored
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Closes: mesa/mesa#8918 Cc: mesa-stable Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!23095> (cherry picked from commit 5be8acc1)
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We only support 32-bit versions of ufind_msb, find_lsb, and bit_count, so we need to lower them via nir_lower_int64. Previously, we were failing to do so on platforms older than Icelake and let those operations fall through to nir_lower_bit_size, which used a callback to determine it should lower them for bit_size != 32. However, that pass only emulates small bit-size operations by promoting them to supported, larger bit-sizes (i.e. 16-bit using 32-bit). It doesn't support emulating larger operations (i.e. 64-bit using 32-bit). So nir_lower_bit_size would just u2u32 the 64-bit source, causing us to flat ignore half of the bits. Commit 78a195f2 (intel/compiler: Postpone most int64 lowering to brw_postprocess_nir) provoked this bug on Icelake and later as well, by moving the nir_lower_int64 handling for ufind_msb until late in compilation, allowing it to reach nir_lower_bit_size which broke it. To fix this, we always set int64 lowering for these opcodes, and also correct the nir_lower_bit_size callback to ignore 64-bit operations. Cc: mesa-stable Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <mesa/mesa!23123> (cherry picked from commit a2d384a5)
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Some GPUs can only handle 32-bit find_lsb. Cc: mesa-stable Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <mesa/mesa!23123> (cherry picked from commit 9293d8e6)
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VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT is also set in all memory types of integrated GPUs. This flag means that memory will be allocated in the most efficient place for the GPU to access, which is true in integrated GPUs. However, this was causing ANV_BO_ALLOC_WRITE_COMBINE to be set in integrated GPUs in the block right below when allocating in the non-cached memory type. But the comment only talks about lmem, so to still keep the write combine behavior for iGPUs it was used VkMemoryPropertyFlags in mmap_calc_flags(). Additionally, this was causing anv_bo.has_implicit_ccs to always be set, which could change the expected behavior of anv_BindImageMemory2() in MTL. Fixes: fbd32a04 ("anv: add a third memory type for LLC configuration") added a new heap Fixes: 582bf4d9 ("anv: flag BO for write combine when CPU visible and potentially in lmem") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!22483> (cherry picked from commit a6c5746b)
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Fixes an assertion with test_amplification_shader in vkd3d-proton. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!23057> (cherry picked from commit b83ce03a)
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On RDNA1&2, the driver needs to support both NGG and legacy for primitives generated query because we can't know that before starting queries. To get the query pool results, we check the availability bit wrote by the SAMPLE_STREAMOUTSTATS packet but the GDS copy was emitted after, which means the availability bit might be TRUE before the GDS copy is actually done. Fix this by emitting the GDS copy before to ensure the availability is TRUE for both results. This fixes recent updates in dEQP-VK.transform_feedback.primitives_generated_query.* because the tests no longer wait for the fence. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!23080> (cherry picked from commit 9ba41ed7)
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