- Dec 16, 2021
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Consider the GPIO controller offset (from "gpio-ranges") to compute the maximum GPIO line number. This fixes an issue where gpio-ranges uses a non-null offset. e.g.: gpio-ranges = <&pinctrl 6 86 10> In that case the last valid GPIO line is not 9 but 15 (6 + 10 - 1) Cc: stable@vger.kernel.org Fixes: 67e2996f ("pinctrl: stm32: fix the reported number of GPIO lines per bank") Reported-by:Christoph Fritz <chf.fritz@googlemail.com> Signed-off-by:
Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20211215095808.621716-1-fabien.dessenne@foss.st.com Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Dec 09, 2021
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...and gpio-ranges pinctrl-bcm2835 is a combined pinctrl/gpio driver. Currently the gpio side is registered first, but this breaks gpio hogs (which are configured during gpiochip_add_data). Part of the hog initialisation is a call to pinctrl_gpio_request, and since the pinctrl driver hasn't yet been registered this results in an -EPROBE_DEFER from which it can never recover. Change the initialisation sequence to register the pinctrl driver first. This also solves a similar problem with the gpio-ranges property, which is required in order for released pins to be returned to inputs. Fixes: 73345a18 ("pinctrl: bcm2835: Pass irqchip when adding gpiochip") Signed-off-by:
Phil Elwell <phil@raspberrypi.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211206092237.4105895-2-phil@raspberrypi.com Signed-off-by:
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- Nov 24, 2021
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When eint virtual eint number is greater than gpio number, it maybe produce 'desc[eint_n]' size globle-out-of-bounds issue. Signed-off-by:
Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20211110071900.4490-2-zhiyong.tao@mediatek.com Signed-off-by:
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- Nov 16, 2021
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The downstream TLMM binding covers a group of TLMM-related hardware blocks, but the upstream binding only captures the particular block related to controlling the TLMM pins from an OS. In the translation of the driver from downstream, the offset of 0x100000 was lost for the UFS and SDC pingroups. Fixes: d5d348a3 ("pinctrl: qcom: Add SM8350 pinctrl driver") Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20211104170835.1993686-1-bjorn.andersson@linaro.org Signed-off-by:
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An earlier bugfix removed a duplicate field initializer in a macro, but it seems that this came back with the following update: drivers/pinctrl/tegra/pinctrl-tegra194.c:1341:28: error: initialized field overwritten [-Werror=override-init] 1341 | .drv_reg = ((r)), \ | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:1392:41: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y' 1392 | #define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1631:17: note: in expansion of macro 'drive_touch_clk_pcc4' 1631 | drive_##pg_name, \ | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1636:9: note: in expansion of macro 'PINGROUP' 1636 | PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), | ^~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1341:28: note: (near initialization for 'tegra194_groups[0].drv_reg') 1341 | .drv_reg = ((r)), \ | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:1392:41: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y' 1392 | #define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1631:17: note: in expansion of macro 'drive_touch_clk_pcc4' 1631 | drive_##pg_name, \ | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1636:9: note: in expansion of macro 'PINGROUP' 1636 | PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), | ^~~~~~~~ Remove it again. Fixes: 613c0826 ("pinctrl: tegra: Add pinmux support for Tegra194") Fixes: 92cadf68 ("pinctrl: tegra: pinctrl-tegra194: Do not initialise field twice") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20211104133645.1186968-1-arnd@kernel.org Signed-off-by:
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It has been observed that dual edge triggered wakeirq GPIOs on SDM845 doesn't trigger interrupts on the falling edge. Enabling wakeirq_dual_edge_errata for SDM845 indicates that the PDC in SDM845 suffers from the same problem described, and worked around, by Doug in 'c3c0c2e1 ("pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180")', so enable the workaround for SDM845 as well. The specific problem seen without this is that gpio-keys does not detect the falling edge of the LID gpio on the Lenovo Yoga C630 and as such consistently reports the LID as closed. Fixes: e35a6ae0 ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20211102034115.1946036-1-bjorn.andersson@linaro.org Signed-off-by:
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apple_gpio_irq_type can possibly return -EINVAL which triggers the following compile error with gcc 9 because the type no longer fits into the mask. drivers/pinctrl/pinctrl-apple-gpio.c: In function 'apple_gpio_irq_set_type': ././include/linux/compiler_types.h:335:38: error: call to '__compiletime_assert_289' declared with attribute error: FIELD_PREP: value too large for the field 335 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ [...] drivers/pinctrl/pinctrl-apple-gpio.c:294:7: note: in expansion of macro 'FIELD_PREP' 294 | FIELD_PREP(REG_GPIOx_MODE, irqtype)); | ^~~~~~~~~~ Fix this by making the return value always valid and instead checking for REG_GPIOx_IN_IRQ_OFF in apple_gpio_irq_set_type and return -EINVAL from there. Fixes: a0f160ff ("pinctrl: add pinctrl/GPIO driver for Apple SoCs") Signed-off-by:Sven Peter <sven@svenpeter.dev> Reviewed-by:
Joey Gouly <joey.gouly@arm.com> Link: https://lore.kernel.org/r/20211101150640.46553-1-sven@svenpeter.dev Signed-off-by:
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mt7620.h, included by pinctrl-mt7620.c, mentions MT762X_SOC_MT7628AN declared in ralink_regs.h. Fixes: 745ec436 ("pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file") Cc: stable@vger.kernel.org Signed-off-by:
Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20211031064046.13533-1-sergio.paracuellos@gmail.com Signed-off-by:
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When PINCTRL_QCOM_SPMI_PMIC or PINCTRL_QCOM_SSBI_PMIC is selected, and GPIOLIB is not selected, Kbuild gives the following warnings: WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP Depends on [n]: GPIOLIB [=n] Selected by [y]: - PINCTRL_QCOM_SPMI_PMIC [=y] && PINCTRL [=y] && (ARCH_QCOM [=n] || COMPILE_TEST [=y]) && OF [=y] && SPMI [=y] WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP Depends on [n]: GPIOLIB [=n] Selected by [y]: - PINCTRL_QCOM_SSBI_PMIC [=y] && PINCTRL [=y] && (ARCH_QCOM [=n] || COMPILE_TEST [=y]) && OF [=y] This is because these config options enable GPIOLIB_IRQCHIP without selecting or depending on GPIOLIB, despite GPIOLIB_IRQCHIP depending on GPIOLIB. These unmet dependency bugs were detected by Kismet, a static analysis tool for Kconfig. Please advise if this is not the appropriate solution. Signed-off-by:
Julian Braha <julianbraha@gmail.com> Link: https://lore.kernel.org/r/20211029004610.35131-1-julianbraha@gmail.com Signed-off-by:
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Instead of returning const pointer from tegra_pinctrl_get_group() the return value is being casted. This change helps return const pointer. Signed-off-by:
Prathamesh Shete <pshete@nvidia.com> Signed-off-by:
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On some Lenovo AMD Gen2 platforms the IRQ for the SCI and pinctrl drivers are shared. Due to how the s2idle loop handling works, this case needs an extra explicit check whether the interrupt was caused by SCI or by the GPIO controller. To fix this rework the existing IRQ handler function to function as a checker and an IRQ handler depending on the calling arguments. BugLink: drm/amd#1738 Reported-by:
Joerie de Gram <j.de.gram@gmail.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20211101014853.6177-2-mario.limonciello@amd.com Signed-off-by:
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- Oct 26, 2021
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This driver adds support for the pinctrl / GPIO hardware found on some Apple SoCs. Co-developed-by:
Stan Skowronek <stan@corellium.com> Signed-off-by:
Hector Martin <marcan@marcan.st> Reviewed-by:
Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211026175815.52703-5-joey.gouly@arm.com Signed-off-by:
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Fix warnings are errors caused by commit a42c7d95 ("pinctrl: tegra: Use correct offset for pin group"). Signed-off-by:
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- Oct 25, 2021
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Adding a configuration menu to hold many Intel pin control drivers helps to make the display more concise. Acked-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
Cai Huoqing <caihuoqing@baidu.com> Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Function tegra_pinctrl_gpio_request_enable() and tegra_pinctrl_gpio_disable_free() uses pin offset instead of group offset, causing the driver to use wrong offset to enable gpio. Add a helper function tegra_pinctrl_get_group() to parse the pin group and determine correct offset. Signed-off-by:
Kartik K <kkartik@nvidia.com> Signed-off-by:
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- Oct 24, 2021
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I got memory leak as follows when doing fault injection test: unreferenced object 0xffff888020a7a680 (size 64): comm "i2c-mcp23018-41", pid 23090, jiffies 4295160544 (age 8.680s) hex dump (first 32 bytes): 00 48 d3 1e 80 88 ff ff 00 1a 56 c1 ff ff ff ff .H........V..... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<0000000083c79b35>] kmem_cache_alloc_trace+0x16d/0x360 [<0000000051803c95>] pinctrl_init_controller+0x6ed/0xb70 [<0000000064346707>] pinctrl_register+0x27/0x80 [<0000000029b0e186>] devm_pinctrl_register+0x5b/0xe0 [<00000000391f5a3e>] mcp23s08_probe_one+0x968/0x118a [pinctrl_mcp23s08] [<000000006112c039>] mcp230xx_probe+0x266/0x560 [pinctrl_mcp23s08_i2c] If pinctrl_claim_hogs() fails, the 'pindesc' allocated in pinctrl_register_one_pin() need be freed. Cc: stable@vger.kernel.org Reported-by:Hulk Robot <hulkci@huawei.com> Fixes: 950b0d91 ("pinctrl: core: Fix regression caused by delayed work for hogs") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20211022014323.1156924-1-yangyingliang@huawei.com Signed-off-by:
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Update the pinctrl-bcm2835 driver to support being built as as a module by converting it to a module_platform_driver() with the appropriate module license, authors and description. Signed-off-by:
Nicolas Saenz Julienne <nsaenz@kernel.org> Link: https://lore.kernel.org/r/20211019221127.1953001-1-f.fainelli@gmail.com Signed-off-by:
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Ignore the same function with multiple groups. Fix a typo in error print. Fixes: 1948d5c5 ("pinctrl: Add pinmux & GPIO controller driver for a new SoC") Signed-off-by:
Rahul Tanwar <rtanwar@maxlinear.com> Link: https://lore.kernel.org/r/20211020093815.20870-1-rtanwar@maxlinear.com Signed-off-by:
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This change adds pinmux table entries for Tegra194 Signed-off-by:
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Update lpdr pin-property for supported pins. lpdr property help disable most basic driver fingers leaving only minimal base driver finger. Signed-off-by:
Suresh Mangipudi <smangipudi@nvidia.com> Signed-off-by:
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This commit includes pinctrl driver for Mediatek MT7986 The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by:
Sam Shih <sam.shih@mediatek.com> Acked-by:
Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20211022124036.5291-3-sam.shih@mediatek.com Signed-off-by:
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On lan966x platform when the switch gets reseted then also the sgpio gets reseted. The fix for this is to extend also the sgpio driver to call the reset driver which will be reseted only once by the first driver that is probed. Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by:
Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20211018085754.1066056-3-horatiu.vultur@microchip.com Signed-off-by:
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- Oct 17, 2021
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spmi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the spmi-mpp code to correct this issue. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,spmi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by:
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ssbi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the ssbi-mpp code to correct this issue. Signed-off-by:
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The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,ssbi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by:
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Add pinctrl data for ExynosAuto v9 SoC. - GPA0, GPA1: 10, External wake up interrupt - GPQ0: 2, XbootLDO, Speedy PMIC I/F - GPB0, GPB1, GPB2, GPB3: 29, I2S 7 CH - GPF0, GPF1, GPF2, GPF3,GPF4, GPF5, GPF6, GPF8: 52, FSYS - GPG0, GPG1, GPG2, GPG3: 25, GPIO x 24, SMPL_INT - GPP0, GPP1, GPP2, GPP3, GPP4, GPP5: 48, USI 12 CH Signed-off-by:
Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20211008091443.44625-2-chanho61.park@samsung.com Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211017171912.5044-1-krzysztof.kozlowski@canonical.com Signed-off-by:
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- Oct 16, 2021
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Some systems such as the Microsoft Surface Laptop 4 leave interrupts enabled and configured for use in sleep states on boot, which cause unexpected behaviour such as spurious wakes and failed resumes in s2idle states. As interrupts should not be enabled until they are claimed and explicitly enabled, disabling any interrupts mistakenly left enabled by firmware should be safe. Signed-off-by:
Sachi King <nakato@nakato.io> Link: https://lore.kernel.org/r/20211009033240.21543-1-nakato@nakato.io Signed-off-by:
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- Oct 15, 2021
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Geert Uytterhoeven authored
Add a "sh_pfc: " prefix to common checker output that is not yet prefixed by a subdriver-specific prefix ("<SoC-part-number>_pfc: "), for easier grepping. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9cf1dc9f895dc5fa74125dabddfe46fecf438b4f.1633615652.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be checked. In addition, sh_pfc_check_bias_reg() does not handle such entries. Fix this by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Signed-off-by:
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Geert Uytterhoeven authored
Move the check for overlapping drive register fields from sh_pfc_check_drive_reg() to sh_pfc_check_reg(), so it can be used for other register types, too. This requires passing the covered register bits to sh_pfc_check_reg(). Signed-off-by:
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Geert Uytterhoeven authored
The GENMASK(h, l) macro creates a contiguous bitmask starting at bit position @l and ending at position @h, inclusive. This did not trigger any error checks, as the individual register fields cover at most 3 of the 4 available bits. Fixes: 08df16e0 ("pinctrl: sh-pfc: checker: Add drive strength register checks") Signed-off-by:
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Geert Uytterhoeven authored
If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be saved/restored during PSCI system suspend. Fortunately this does not trigger on any supported system yet, as PSCI is only used on R-Car Gen3 and RZ/G2 systems, which all have separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers. Avoid this ever becoming a problem by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Note that a register controlling both pull-up and pull-down pins would be saved and restored twice, which is harmless. Signed-off-by:
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Andrey Gusakov authored
This adds pins, groups, and functions for MediaLB devices on Renesas R-Car H3 and M3-W/N SoCs. Signed-off-by:
Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by:
Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by:
LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by:
Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211007200250.20661-1-nikita.yoush@cogentembedded.com [geert: Fix automotive handling] Signed-off-by:
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- Oct 13, 2021
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Signed-off-by:
Du Huanpeng <dhu@hodcarrier.org> Link: https://lore.kernel.org/r/1633879405-11658-1-git-send-email-dhu@hodcarrier.org Signed-off-by:
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When resuming from low power, the driver attempts to restore the configuration of some pins. This is done by a call to: stm32_pinctrl_restore_gpio_regs(struct stm32_pinctrl *pctl, u32 pin) where 'pin' must be a valid pin value (i.e. matching some 'groups->pin'). Fix the current implementation which uses some wrong 'pin' value. Fixes: e2f3cf18 ("pinctrl: stm32: add suspend/resume management") Signed-off-by:
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Since the 'st,package' property is optional, outputting the "No package detected" warning-level log when the property is absent is unsuitable. Remove that log. Signed-off-by:
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This reverts commit a49d784d. The updated binding was wrong / invalid and has been reverted. There isn't any upstream kernel DTS using it and Broadcom isn't known to use it neither. There is close to zero chance this will cause regression for anyone. Actually in-kernel bcm5301x.dtsi still uses the old good binding and so it's broken since the driver update. This revert fixes it. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20211008205938.29925-3-zajec5@gmail.com Signed-off-by:
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Add pin configuration and pinmux support for UniPhier NX1 SoC. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1633518606-8298-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by:
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Add extra audio I/O pinmux setting for LD11, LD20 and PXs3 SoCs. Signed-off-by:
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