- Jun 15, 2022
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The bw_fixed library performs a lot of the mathematical operations involving fixed-point arithmetic and the conversion of integers to fixed-point representation. As fixed-point representation is the base foundation of the DML calcs operations, this unit tests intend to assure the proper functioning of the basic mathematical operations of fixed-point arithmetic, such as multiplication, conversion from fractional to fixed-point number, and more. Co-developed-by:
Tales Aparecida <tales.aparecida@gmail.com> Signed-off-by:
Magali Lemes <magalilemes00@gmail.com> Co-developed-by:
Maíra Canal <maira.canal@usp.br> Signed-off-by:
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Maíra Canal authoredThe macros defined at bw_fixed are important mathematical definitions, specifying masks to get the fractional part and the maximum and minimum values of I64. In order to enable unit tests for bw_fixed, it is relevant to have access to those macros. This commit moves the macros to the header file, making it accessible to future unit tests. Signed-off-by: -
Maíra Canal authored
KUnit unifies the test structure and provides helper tools that simplify the development of tests. Basic use case allows running tests as regular processes, which makes easier to run unit tests on a development machine and to integrate the tests in a CI system. This commit introduces a basic unit test to one part of the Display Mode Library: display_mode_lib, in order to introduce the basic structure of the tests on the DML. Signed-off-by:
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- Jun 01, 2022
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Candice Li authored
Fix misleading indentation and add ras unsupported checking for gfx ras late init. Fixes: fd3fb1b9 ("drm/amdgpu: Resolve RAS GFX error count issue after cold boot on Arcturus") Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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This symbol is not used outside of gfx_v11_0.c, so marks it static. Fixes the following w1 warning: drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:1945:6: warning: no previous prototype for function 'gfx_v11_0_rlc_stop' [-Wmissing-prototypes]. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
sunliming <sunliming@kylinos.cn> Signed-off-by:
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Fixes the following w1 warning: drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:5873:2: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough]. Reported-by:
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This patch will fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7.0. NBIO v7.7.0 uses a new reg function -- Common SDMA to allow a common doorbell range for all SDMA queues, this is different to the old NBIO version. This patch will add configuration for CSDMA and enable SDMA doorbell function. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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This patch will add CSDMA reg offsets for NBIO v7.7.0 Signed-off-by:
Roman Li <roman.li@amd.com> Acked-by:
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APU required to issue the enable GFX IMU message after IMU reset. Signed-off-by:
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GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU. Signed-off-by:
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Update MP v13_0_4 register macro for SMU message v2: squash in missed case (Alex) Signed-off-by:
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This adds mmhub v3_0_1 ip block support v2: rebase (Alex) Signed-off-by:
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Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0. v2: squash in updates (Alex) Signed-off-by:
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[Why] Wrong fb offset results in dmub f/w errors and white screen. [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 [How] Read aper_base from mmhub because GC is off by default v2: use BAR for passthrough (Alex) Signed-off-by:
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Switch to use the callback function to poll the reset status on IMU. Because it will have different sequency on other ASICs. v2: drop unused variable (Alex) Acked-by:
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Candice Li authored
Adjust the sequence for ras late init and separate ras reset error status from query status. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com>
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Dillon Varone authored
[Why?] On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads DMUB, and driver does not reload as it appears to be initialized already. [How?] Add a check for the DAL_FW bit to ensure that loaded FW is from driver and not VBIOS. Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Charlene Liu authored
[why] Use correct clock source initialization routine for DCN32/321 Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Dillon Varone authored
[WHY&HOW] Change criteria for setting DTO source value, and always set it regardless of the signal type. Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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stanley yang authored
Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Acked-by:
Lijo Lazar <lijo.lazar@amd.com>
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Aurabindo Pillai authored
Disable idle optimizations until SMU can handle them to prevent DMUB timeout and subsequent system freeze Signed-off-by:
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Aurabindo Pillai authored
Signed-off-by:
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stanley yang authored
Fix aldebaran ras supported check on SRIOV guest side, the previous check conditicon block all ras feature on baremetal Signed-off-by:
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Alvin Lee authored
Add support for watermark table transfers. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Dillon Varone authored
Fixes to enable higher rate timings for DCN3.2.x. Signed-off-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Dillon Varone authored
[WHY?] DCN321 does not support FCLK DPM, and thus it should not send messages to PMFW regarding it. Signed-off-by:
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Huang Rui authored
IMU has two work mode such as debug mode and mission mode. Current GC v11_0_0 is using the debug mode. Acked-by:
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- May 31, 2022
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Eric Bernstein authored
Use DTBCLK for valid pixel clock generation Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Acked-by:
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Alvin Lee authored
[Description] Need to add inst 5 for clk_src_regs because there are 5 PHY instances in DCN32 & DCN321. Signed-off-by:
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Dillon Varone authored
[Description] Add USBC connector ID to align with new VBIOS parsing. Add seperate DCN321 link encoder due to different PHY version affecting DP ALT related registers. Signed-off-by:
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Aurabindo Pillai authored
GFX11 IP introduces new tiling mode. Various combinations of DCC settings are possible and the most preferred settings must be exposed for optimal use of the hardware. add_gfx11_modifiers() is based on recommendation from Marek for the preferred tiling modifier that are most efficient for the hardware. v2: microtiling fix noticed by Marek v3: keep Z tiling check Signed-off-by:
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Kenneth Feng authored
align the cg and pg settings between gc_v11_0 and gc_v11_2 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why&How] Add DCN32 to IP discovery to enable automatic initialization of AMDGPU Display Manager Signed-off-by:
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Aurabindo Pillai authored
Add Display Manager specific changes for DCN3.2.x. DM handles the interaction between the core DC modesetting code and the drm modesetting infrastructure. Signed-off-by:
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Jack Xiao authored
fix mes11 api interface. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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- May 30, 2022
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[Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by:
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Add core DC support for DCN 3.2.x. v2: squash in fixup (Alex) Signed-off-by:
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Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by:
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Aurabindo Pillai authored
DML is required for display configuration modelling for things like bandwidth management and validation. Signed-off-by:
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Aurabindo Pillai authored
Add support for the GPIO changes for DCN3.2.x. Signed-off-by:
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