Add DSI support for SC8280XP
SC8280XP has 2 dsi controllers. I have a HUAWEI Matebook E Go which is a 2-in-1 tablet powered by sc8280xp. It has a 12.4 inch dual-dsc dsi panel driven by himax hx83121a IC(the same as samsung glaxy tab s7 fe). I managed to get a panel driver using lmdpdg with samsung's opensource dt(single dsc) but sadly there is no mainline dsi support for sc8280xp. I guess sc8280xp's dsi controllers might be similar to sm8350's and had some try based on sm8350's source.
Kernel source from steev/linux.
First is to add dsi description in sc8280xp.dtsi:
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 94c45da63..fa19422d4 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4153,6 +4153,20 @@ mdss0_intf0_out: endpoint {
};
};
+ port@1 {
+ reg = <1>;
+ mdss0_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ mdss0_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+
port@4 {
reg = <4>;
mdss0_intf4_out: endpoint {
@@ -4283,6 +4297,202 @@ opp-810000000 {
};
};
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <4>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ phys = <&mdss_dsi0_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ dsi0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* TODO: opp-187500000 should work with
+ * &rpmhpd_opp_low_svs, but one some of
+ * sm8350_hdk boards reboot using this
+ * opp.
+ */
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&mdss0_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sm8350-dsi-phy-5nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss_dsi1: dsi@ae96000 {
+ compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <5>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc0 DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi1_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ phys = <&mdss_dsi1_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ dsi1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* TODO: opp-187500000 should work with
+ * &rpmhpd_opp_low_svs, but one some of
+ * sm8350_hdk boards reboot using this
+ * opp.
+ */
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&mdss0_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,sm8350-dsi-phy-5nm";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96900 0 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
mdss0_dp1: displayport-controller@ae98000 {
compatible = "qcom,sc8280xp-dp";
reg = <0 0xae98000 0 0x200>,
@@ -4557,10 +4767,9 @@ dispcc0: clock-controller@af00000 {
<&mdss0_dp2_phy 1>,
<&mdss0_dp3_phy 0>,
<&mdss0_dp3_phy 1>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
+
power-domains = <&rpmhpd SC8280XP_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
Then I add a new sc8280xp-huawei-matebook-e-go.dts and descibe the panel like this:
&mdss_dsi0 {
status = "okay";
vdda-supply = <&vreg_l3b>;
panel@0 {
compatible = "mdss,hx83121-ppc357db11-wqxga";
reg = <0>;
reset-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
status = "okay";
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&panel_in>;
};
&mdss_dsi0_phy {
vdds-supply = <&vreg_l6b>;
status = "okay";
};And I get sc8280xp's dsi ver is 0x20050001
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 1f98ff74c..9c9f6a692 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -277,6 +277,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0,
&sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_1,
+ &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0,
&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0,
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 43f0dd74e..8dbe65403 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -26,6 +26,7 @@
#define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000
#define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001
#define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000
+#define MSM_DSI_6G_VER_MINOR_V2_5_1 0x20050001
#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000
#define MSM_DSI_6G_VER_MINOR_V2_7_0 0x20070000But dsi_phy seems not work well, I add some pr_err() to debug...
In clk-rcg2.c
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 5183c74b0..0934403ef 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -787,6 +787,8 @@ static int clk_pixel_determine_rate(struct clk_hw *hw,
request = (req->rate * frac->den) / frac->num;
src_rate = clk_hw_round_rate(req->best_parent_hw, request);
+ pr_err("%s:request dsi pixel rate: %ld, parent src rate: %ld\n", __func__, request, src_rate);
+
if ((src_rate < (request - delta)) ||
(src_rate > (request + delta)))
continue;
@@ -795,7 +797,7 @@ static int clk_pixel_determine_rate(struct clk_hw *hw,
req->rate = (src_rate * frac->num) / frac->den;
return 0;
}
-
+ pr_err("%s:no src rate matched!\n",__func__);
return -EINVAL;
}And seems the dsi_phy was trying to set the pixel clock again and again:
matebook-e-go kernel: [ 3.800455] clk_pixel_determine_rate:request dsi pixel rate: 751594666, parent src rate: 563695996
matebook-e-go kernel: [ 3.800458] clk_pixel_determine_rate:request dsi pixel rate: 1268316000, parent src rate: 845543994
matebook-e-go kernel: [ 3.800462] clk_pixel_determine_rate:request dsi pixel rate: 634158000, parent src rate: 563695996
matebook-e-go kernel: [ 3.800465] clk_pixel_determine_rate:request dsi pixel rate: 281848000, parent src rate: 281847998
matebook-e-go kernel: [ 3.800748] set disp0_cc_mdss_byte0_div_clk_src parent disp0_cc_mdss_byte0_clk_src rate: 105693000
matebook-e-go kernel: [ 3.800782] set disp0_cc_mdss_byte0_clk_src parent dsi0_phy_pll_out_byteclk rate: 105693000
matebook-e-go kernel: [ 3.800809] set dsi0_phy_pll_out_byteclk parent dsi0_pll_bit_clk rate: 845544000
matebook-e-go kernel: [ 3.800925] DSI PLL0 rate=845544000, parent's=19200000
matebook-e-go kernel: [ 3.800928] SSC not enabled
matebook-e-go kernel: [ 3.800972] DSI PLL0 returning vco rate = 845543994, dec = 16, frac = 13d7
matebook-e-go kernel: [ 3.873341] usb 5-1: New USB device found, idVendor=152d, idProduct=0579, bcdDevice=14.05
matebook-e-go kernel: [ 3.873373] usb 5-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
matebook-e-go kernel: [ 3.873384] usb 5-1: Product: FanxiangSSD
matebook-e-go kernel: [ 3.873393] usb 5-1: Manufacturer: Fanxiang
matebook-e-go kernel: [ 3.873400] usb 5-1: SerialNumber: 0000000001C3
matebook-e-go kernel: [ 3.911146] scsi host0: uas
matebook-e-go kernel: [ 3.911271] usbcore: registered new interface driver uas
matebook-e-go kernel: [ 3.933256] scsi 0:0:0:0: Direct-Access Fanxiang DISK00 1405 PQ: 0 ANSI: 6
matebook-e-go kernel: [ 3.934835] set dsi0_phy_pll_out_byteclk parent dsi0_pll_bit_clk rate: 1691088000
matebook-e-go kernel: [ 3.934852] set dsi0_pll_bit_clk parent dsi0_pll_out_div_clk rate: 1691088000
matebook-e-go kernel: [ 3.934863] set dsi0_pll_out_div_clk parent dsi0vco_clk rate: 1691088000
matebook-e-go kernel: [ 3.934866] set dsi0vco_clk parent bi_tcxo rate: 1691088000
matebook-e-go kernel: [ 3.934934] DSI PLL0 rate=1691088000, parent's=19200000
matebook-e-go kernel: [ 3.934937] SSC not enabled
matebook-e-go kernel: [ 3.934980] DSI PLL0 returning vco rate = 1691087988, dec = 2c, frac = 27ae
matebook-e-go kernel: [ 3.935050] clk_pixel_determine_rate:request dsi pixel rate: 751594666, parent src rate: 563695996
matebook-e-go kernel: [ 3.935053] clk_pixel_determine_rate:request dsi pixel rate: 1268316000, parent src rate: 845543994
matebook-e-go kernel: [ 3.935055] clk_pixel_determine_rate:request dsi pixel rate: 634158000, parent src rate: 563695996
matebook-e-go kernel: [ 3.935057] clk_pixel_determine_rate:request dsi pixel rate: 281848000, parent src rate: 281847998And it repeated many times until drm time out. If I open drm.debug=0x6, I get thousands of them:
matebook-e-go kernel: [ 17.649060] [drm:dsi_host_irq [msm]] isr=0xab20aa00, id=0
matebook-e-go kernel: [ 17.649082] [drm:dsi_intr_ctrl [msm]] intr=a920aa00 enable=0
matebook-e-go kernel: [ 17.649114] [drm:dsi_intr_ctrl [msm]] intr=ab20aa00 enable=1
matebook-e-go kernel: [ 17.649147] [drm:dsi_host_irq [msm]] isr=0xab20aa00, id=0
matebook-e-go kernel: [ 17.649170] [drm:dsi_intr_ctrl [msm]] intr=a920aa00 enable=0
matebook-e-go kernel: [ 17.649207] [drm:dsi_intr_ctrl [msm]] intr=ab20aa00 enable=1
matebook-e-go kernel: [ 17.649233] [drm:dsi_host_irq [msm]] isr=0xab20aa00, id=0
matebook-e-go kernel: [ 17.649255] [drm:dsi_intr_ctrl [msm]] intr=a920aa00 enable=0
matebook-e-go kernel: [ 17.649287] [drm:dsi_intr_ctrl [msm]] intr=ab20aa00 enable=1
matebook-e-go kernel: [ 17.649320] [drm:dsi_host_irq [msm]] isr=0xab20aa00, id=0
matebook-e-go kernel: [ 17.649342] [drm:dsi_intr_ctrl [msm]] intr=a920aa00 enable=0You can find my panel driver here.
Thank you for your attention to this issue. Any guidance or assistance you can provide would be greatly appreciated.
Activity
Hi @matalama80td3l, thanks for reaching out.
Can you be more specific about the exact error that you are seeing once "drm time out"? Is there any sort of corruption on screen (if so: share a photo) or does it remain black?
It looks like the linked panel driver was not set up for DSC compression nor dual-DSI. Can this panel function without either of those? At least the mode seems to use the native resolution (2.5k) but at 60 instead of 120Hz. I haven't calculated whether that is possible without DSC nor dual-DSI.
There are quite a few things to consider about this dual-DSI dual-DSC video-mode setup. Most notably that:
- Upstream kernel support for video-mode DSC has not been validated nor merged yet;
- Support for dual-DSI on newer SoCs with "active-CTL" (different way to configure DPU hardware blocks) has not been merged yet;
- Support for dual-DSC with a dual-DSI setup is likewise also not working out of the box. I have sent some patches to get started on this, some of which have already been merged: https://lore.kernel.org/linux-arm-msm/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-0-78ae3ee9a697@somainline.org/
- lmdpdg has support for generating panel drivers with DSC, but not yet dual-DSI. You can consult the panel driver in the commit history linked below to get a glimpse of how that would look.
Your best bet is to start looking at the patches in the history of https://github.com/somainline/linux/commits/92a6d753fa81131cf4bfea10c58b82325379ae93, which contains fixes for most of the above except video-mode DSC 1. These commits provide a working 4k@120Hz panel on a Sony Xperia 1 III, which is a command-mode panel connected over dual-DSI and powered by two DSC encoders. These patches are a small part of my development tree, and I'll let you know when there's a cleaner branch available that's easier to pick. There's a higher priority on sending the valid patches from that tree upstream first, though.
Related/duplicate issues:
-
you'll have to integrate video-mode DSC support separately based on two disjoint series on the lists: https://lore.kernel.org/linux-arm-msm/20240403-msm-drm-dsc-dsi-video-upstream-v1-0-db5036443545@linaro.org/ and https://lore.kernel.org/linux-arm-msm/20231114225857.19702-1-jonathan@marek.ca/.
Edited by Marijn SuijtenThanks for your help Marijn!
- Panel initialised failed so it kept black. DSI pixel clock was caculated many times so I guess some clocks had not been set up properly.
- This panel must work with dsc and video mode, but imo dual dsc and dual dsi is not a must. I'm working on the same panel of #52 and in this case sm7325 only has 1 dsi controller.
- Thank you for pointing out that my panel driver is not a DSC one. But I'm quite confused why I got a wrong panel driver from samsung's dt with lmdpdg. I'll ask for the panel driver in #52 later.
- I know there's still problems in DSC +video_mode condition but I'm still far from it because my panel has not been initialised... I'm not confident about my hacks of using sm8350's configuration to configure sc8280xp's dsi
-
well I generated the panel driver before lmdpdg supported dsc…
That's not a problem, but since it's there now the request is to regen and try again
- Panel initialised failed so it kept black. DSI pixel clock was caculated many times so I guess some clocks had not been set up properly.
This might be fine due to how the clock framework calls some of these functions multiple times to find a rate that satisfies multiple clock consumers, or find a configuration/parenting strategy that comes closest to the requested rate, IIRC.
- This panel must work with dsc and video mode, but imo dual dsc and dual dsi is not a must. I'm working on the same panel of #52 and in this case sm7325 only has 1 dsi controller.
Do you know what commands to send (if it's the same controller after all) to allow it to function with 1 DSI link? Otherwise it might be possible to have only half the screen working.
- I'll ask for the panel driver in #52 later.
Maybe that helps to understand the command differences between single- and dual-DSI?
- I know there's still problems in DSC +video_mode condition but I'm still far from it because my panel has not been initialised... I'm not confident about my hacks of using sm8350's configuration to configure sc8280xp's dsi
As suggested above, let's start with regenerating a panel driver that contains a DSC setup. I'd disable both your custom clock debugging and remove
drm.debug=0x6because they're way too spammy to analyze what is actually going wrong. We can pick up debugging from there. Good luck! Hi I just created a new account because Cloudflare blocked me from logging endlessly. I regenerated a new driver and removed the debugs you had mentioned. dmesg_dsc.log Full log here.
I just see many
dsi_err_worker: status=4. It seems mean dsi fifo error.
