<7> [153.788773] i915 0000:00:02.0: [drm] pipe csc: pre offsets: 0x0000 0x0000 0x0000
<7> [153.788777] i915 0000:00:02.0: [drm] pipe csc: coefficients: 0x0000 0x0000 0x0000
<7> [153.788780] i915 0000:00:02.0: [drm] pipe csc: coefficients: 0x0000 0x0000 0x0000
<7> [153.788784] i915 0000:00:02.0: [drm] pipe csc: coefficients: 0x0000 0x0000 0x0000
<7> [153.788787] i915 0000:00:02.0: [drm] pipe csc: post offsets: 0x0000 0x0000 0x0000
<7> [153.788791] i915 0000:00:02.0: [drm] [PLANE:32:plane 1A] fb: [FB:227] 1920x1200 format = NV12 little-endian (0x3231564e) modifier = 0x0, visible: yes
<7> [153.788798] i915 0000:00:02.0: [drm] rotation: 0x1, scaler: -1, scaling_filter: 0
<7> [153.788801] i915 0000:00:02.0: [drm] src: 1920.000000x1200.000000+0.000000+0.000000 dst: 1920x1200+0+0
<7> [153.788807] i915 0000:00:02.0: [drm] [PLANE:59:plane 4A] fb: [FB:227] 1920x1200 format = NV12 little-endian (0x3231564e) modifier = 0x0, visible: no
<7> [153.788812] i915 0000:00:02.0: [drm] rotation: 0x1, scaler: -1, scaling_filter: 0
<7> [153.788933] i915 0000:00:02.0: [drm:intel_psr_disable_locked [i915]] Disabling PSR2
<3> [153.794066] i915 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun: port,transcoder,
<7> [153.810433] i915 0000:00:02.0: [drm:intel_psr_post_plane_update [i915]] Enabling PSR1
<7> [153.811315] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:189:eDP-1]
<7> [153.811517] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:82:pipe A]
<7> [153.835949] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:189:eDP-1] Limiting display bpp to 24 (EDID bpp 24, max requested bpp 36, max platform bpp 36)
<7> [153.836545] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:188:DDI A/PHY A][CRTC:82:pipe A] DP link limits: pixel clock 317250 kHz DSC off max lanes 2 max rate 540000 max pipe_bpp 24 max link_bpp 24.0000
<7> [153.837022] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] DP lane count 2 clock 540000 bpp input 24 compressed 0.0000 link rate required 951750 available 1080000
<7> [153.837432] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [153.837889] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:188:DDI A/PHY A] [CRTC:82:pipe A]
<7> [153.838291] i915 0000:00:02.0: [drm:icl_check_nv12_planes [i915]] Using plane 4A as Y plane for plane 1A
<7> [153.838794] i915 0000:00:02.0: [drm] [CRTC:82:pipe A] enable: yes [fastset]
<7> [153.838803] i915 0000:00:02.0: [drm] active: yes, output_types: EDP (0x100), output format: RGB, sink format: RGB
<7> [153.838810] i915 0000:00:02.0: [drm] cpu_transcoder: A, pipe bpp: 24, dithering: 0
<7> [153.838816] i915 0000:00:02.0: [drm] MST master transcoder: <invalid>
<7> [153.838820] i915 0000:00:02.0: [drm] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [153.838826] i915 0000:00:02.0: [drm] bigjoiner: no, pipes: 0x0
<7> [153.838831] i915 0000:00:02.0: [drm] splitter: disabled, link count 0, overlap 0
<7> [153.838837] i915 0000:00:02.0: [drm] dp m_n: lanes: 2; data_m: 7392460, data_n: 8388608, link_m: 308019, link_n: 524288, tu: 64
<7> [153.838844] i915 0000:00:02.0: [drm] dp m2_n2: lanes: 2; data_m: 0, data_n: 0, link_m: 0, link_n: 0, tu: 0
<7> [153.838851] i915 0000:00:02.0: [drm] fec: disabled, enhanced framing: enabled
<7> [153.838855] i915 0000:00:02.0: [drm] sdp split: disabled
<7> [153.838860] i915 0000:00:02.0: [drm] psr: enabled, selective update: enabled, panel replay: disabled, selective fetch: enabled
<7> [153.838866] i915 0000:00:02.0: [drm] framestart delay: 1, MSA timing delay: 0
<7> [153.838870] i915 0000:00:02.0: [drm] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [153.838876] i915 0000:00:02.0: [drm] DP SDP: VSC, revision 4, length 14
<7> [153.838882] i915 0000:00:02.0: [drm] pixelformat: RGB
<7> [153.838887] i915 0000:00:02.0: [drm] colorimetry: sRGB
<7> [153.838892] i915 0000:00:02.0: [drm] bpc: 0
<7> [153.838896] i915 0000:00:02.0: [drm] dynamic range: VESA range
<7> [153.838901] i915 0000:00:02.0: [drm] content type: Not defined
<7> [153.838906] i915 0000:00:02.0: [drm] vrr: no, vmin: 1271, vmax: 3177, pipeline full: 0, guardband: 72 flipline: 1272, vmin vblank: 1200, vmax vblank: 3105
<7> [153.838913] i915 0000:00:02.0: [drm] requested mode: "1920x1200": 120 317250 1920 1968 2000 2080 1200 1203 1209 1271 0x48 0xa
<7> [153.838921] i915 0000:00:02.0: [drm] adjusted mode: "1920x1200": 120 317250 1920 1968 2000 2080 1200 1203 1209 1271 0x48 0xa
<7> [153.838928] i915 0000:00:02.0: [drm] crtc timings: clock=317250, hd=1920 hb=1920-2080 hs=1968-2000 ht=2080, vd=1200 vb=1200-1271 vs=1203-1209 vt=1271, flags=0xa
<7> [153.838936] i915 0000:00:02.0: [drm] pipe mode: "1920x1200": 120 317250 1920 1968 2000 2080 1200 1203 1209 1271 0x40 0xa
<7> [153.838943] i915 0000:00:02.0: [drm] crtc timings: clock=317250, hd=1920 hb=1920-2080 hs=1968-2000 ht=2080, vd=1200 vb=1200-1271 vs=1203-1209 vt=1271, flags=0xa
<7> [153.838951] i915 0000:00:02.0: [drm] port clock: 540000, pipe src: 1920x1200+0+0, pixel rate 317250
<7> [153.838957] i915 0000:00:02.0: [drm] linetime: 53, ips linetime: 0
<7> [153.838962] i915 0000:00:02.0: [drm] num_scalers: 2, scaler_users: 0x0, scaler_id: -1, scaling_filter: 0
<7> [153.838968] i915 0000:00:02.0: [drm] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [153.838974] i915 0000:00:02.0: [drm] ips: 0, double wide: 0, drrs: 0
<7> [153.838980] i915 0000:00:02.0: [drm] dpll_hw_state: cfgcr0: 0xe001a5, cfgcr1: 0x48, div0: 0x0, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [153.838988] i915 0000:00:02.0: [drm] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [153.838994] i915 0000:00:02.0: [drm] pre csc lut: 0 entries, post csc lut: 0 entries
<7> [153.838999] i915 0000:00:02.0: [drm] output csc: pre offsets: 0x0000 0x0000 0x0000
<7> [153.839005] i915 0000:00:02.0: [drm] output csc: coefficients: 0x0000 0x0000 0x0000
<7> [153.839011] i915 0000:00:02.0: [drm] output csc: coefficients: 0x0000 0x0000 0x0000
<7> [153.839016] i915 0000:00:02.0: [drm] output csc: coefficients: 0x0000 0x0000 0x0000
<7> [153.839021] i915 0000:00:02.0: [drm] output csc: post offsets: 0x0000 0x0000 0x0000
<7> [153.839025] i915 0000:00:02.0: [drm] pipe csc: pre offsets: 0x0000 0x0000 0x0000
<7> [153.839031] i915 0000:00:02.0: [drm] pipe csc: coefficients: 0x0000 0x0000 0x0000
<7> [153.839036] i915 0000:00:02.0: [drm] pipe csc: coefficients: 0x0000 0x0000 0x0000
<7> [153.839041] i915 0000:00:02.0: [drm] pipe csc: coefficients: 0x0000 0x0000 0x0000
<7> [153.839046] i915 0000:00:02.0: [drm] pipe csc: post offsets: 0x0000 0x0000 0x0000
<7> [153.839051] i915 0000:00:02.0: [drm] [PLANE:32:plane 1A] fb: [FB:227] 1920x1200 format = NV12 little-endian (0x3231564e) modifier = 0x0, visible: yes
<7> [153.839061] i915 0000:00:02.0: [drm] rotation: 0x1, scaler: -1, scaling_filter: 0
<7> [153.839066] i915 0000:00:02.0: [drm] src: 1920.000000x1200.000000+0.000000+0.000000 dst: 1920x1200+0+0
<7> [153.839074] i915 0000:00:02.0: [drm] [PLANE:59:plane 4A] fb: [FB:227] 1920x1200 format = NV12 little-endian (0x3231564e) modifier = 0x0, visible: no
<7> [153.839082] i915 0000:00:02.0: [drm] rotation: 0x1, scaler: -1, scaling_filter: 0
<7> [153.839267] i915 0000:00:02.0: [drm:intel_psr_disable_locked [i915]] Disabling PSR1
<7> [153.843723] i915 0000:00:02.0: [drm:intel_psr_post_plane_update [i915]] Enabling PSR2
<7> [153.845396] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:189:eDP-1]
<7> [153.845893] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:82:pipe A]
<7> [153.848166] i915 0000:00:02.0: [drm:drm_mode_setcrtc] [CRTC:82:pipe A]
<7> [153.848319] i915 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.enable (expected yes, found no)
<7> [153.848328] i915 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in hw.active (expected yes, found no)
<7> [153.848334] i915 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in cpu_transcoder (expected 0, found -1)
<7> [153.848341] i915 0000:00:02.0: [drm] [CRTC:82:pipe A] fastset requirement not met in lane_count (expected 2, found 0)