- Nov 06, 2019
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Dylan Baker authored
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- Nov 05, 2019
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Dylan Baker authored
Otherwise if glvnd is not installed systemwide, but only in a prefix, it's headers wont be found. This happens because if it's headers are in /usr/include/ then another dependence will provide the necessary -I arguments and compilation will work. Fixes: 035ec7a2 ("meson: Add support for EGL glvnd") Acked-by: Eric Engestrom <eric@engestrom.ch> (cherry picked from commit 5d085ad0)
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Commit 5847de6e implemented a restriction that applies to ICL, but wrongly marked it as also applying to GLK. Reviewers or MR !1125 pointed this, and the commit history shows removal of GLK to parts of the patch, but it turns there was still a left-over GLK check in the code. This code was breaking some of the i8vec2 tests on GLK, for example: dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2 Removing the GLK check solves the issue for GLK. I don't see a reason on why implementing this restriction would actually break GLK, so there's still more to investigate here since this bug may be affecting ICL+, but let's apply the real GLK fix while we analyze and discuss the other possible issues. Fixes: 5847de6e ("intel/compiler: don't use byte operands for src1 on ICL") BSpec: 3017 Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (cherry picked from commit b57383a9)
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Fixes: 86786999 "aco: implement VGPR spilling" Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> (cherry picked from commit efe737fc)
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Fixes: 86786999 "aco: implement VGPR spilling" Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> (cherry picked from commit 5c7dcb15)
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Fixes: 86786999 "aco: implement VGPR spilling" Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> (cherry picked from commit d97c0bdd)
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The host query reset entry point didn't use the availability offset for performance queries. To fix this, reorder the availability of performance queries to match other queries. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 2b5f30b1 ("anv: implement VK_INTEL_performance_query") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit ee6fbb95)
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In 2ca0d913, we began updating cso_fb->layers to the actual layer count, rather than 0. This fixed cases where we were setting "Force Zero RTA Index Enable" even when doing layered rendering. Sadly, it also broke the check entirely: cso_fb->layers is now 1 for non-layered cases, but the Force Zero RTA Index check was still comparing for 0. Fixes: 2ca0d913 ("iris: Fix framebuffer layer count") (cherry picked from commit fc7b7480)
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Dylan Baker authored
Python has the identity operator `is`, and the equality operator `==`. Using `is` with strings sometimes works in CPython due to optimizations (they have some kind of cache), but it may not always work. Fixes: 96c4b135 ("nir/algebraic: Don't put quotes around floating point literals") Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 717606f9)
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If an app first creates a compute pipeline with VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT set, then re-compile it without that flag, the driver should re-compile the compute shader. Otherwise, it will return the unoptimized one. Fixes: ce188813 ("radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 9ab27647)
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 88d66583)
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The seccomp filter allows read/write, let us make sure nobody can do anything with this. Fixes: cff53da3 "radv: enable secure compile support" Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit 8efb8f55)
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- Nov 01, 2019
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Daniel Schürmann authored
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
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- Oct 31, 2019
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Erik Faye-Lund authored
When switching this to dynamic state, I forgot that this also needs to be emitted when we use a polygon-mode set to lines. Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Fixes: 6d30abb4 ("zink: use dynamic state for line-width") (cherry picked from commit b7674829)
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Alyssa Rosenzweig authored
Build failure reported by i965 CI, triggered by building dynamic pipeloaders with kmsro drivers (besides 'frost). At this point, there's no reason to actually do that -- mesa CI didn't mind -- but let's not break the build. v2: Simplify script. Add extra dependencies for v3d. Fixes: afb0d08c ("pipe-loader: Default to kmsro if probe fails") Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reported-by: Clayton Craft <clayton.a.craft@intel.com> Tested-by: Clayton Craft <clayton.a.craft@intel.com> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> (cherry picked from commit bf153189)
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Faith Ekstrand authored
Otherwise relocations just up and crash. Fixes: a3153162 "anv: Delay allocation of relocation lists" Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 9ef198c5)
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Faith Ekstrand authored
Some of the tests were actually relying on some of those uninitialized bits to be non-zero. In particular, a couple want use_softpin = true. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 9076e9f3)
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Faith Ekstrand authored
Fixes: 731c4adc "anv/allocator: Add support for non-userptr" Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit bb257e18)
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Pierre-Eric Pelloux-Prayer authored
If the DrawBuffer sample count is > 1 and msaa is enabled we must also enable msaa when clearing it. Fixes: ea5b7de1 ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled") Closes: mesa/mesa#1991 Reviewed-by: Marek Olšák <marek.olsak@amd.com> Tested-by: Witold Baryluk <witold.baryluk@gmail.com> (cherry picked from commit 8a723282)
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Got some int->pointer warnings and 20 is not a valid pointer .... Fixes: 2e3a635e "radv: Add an early exit in the secure compile if we already have the cache entries." Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit 6ced684e)
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The resulting locale is not used for Vulkan, and it is not reference counted, giving issues when multiple instances are created. CC: 19.2 19.3 <mesa-stable@lists.freedesktop.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 3e86d553)
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The resulting locale is not used for Vulkan, and it is not reference counted, giving issues when multiple instances are created. CC: 19.2 19.3 <mesa-stable@lists.freedesktop.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 72f858fc)
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The resulting locale is not used for Vulkan, and it is not reference counted, giving issues when multiple instances are created. CC: 19.2 19.3 <mesa-stable@lists.freedesktop.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 344ba56b)
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Pierre-Eric Pelloux-Prayer authored
Until 8bef4df1 the IR (TGSI or NIR) was used in disk_cache driver_flags. This commit restores this features to avoid crashing when switching from one IR to the other. As radeonsi's default is TGSI, I used "driver_flags & 0x8000000 = 0" for TGSI to keep the same driver_flags. Fixes: 8bef4df1 ("radeonsi: add si_debug_options for convenient adding/removing of options") Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit 2afeed30)
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Fixes the following building error: external/mesa/src/amd/compiler/aco_spill.cpp:1768: error: undefined reference to 'aco::lower_to_cssa(aco::Program*, aco::live&, radv_nir_compiler_options const*)' Fixes: 0b8216b2 ("aco: Lower to CSSA") Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> (cherry picked from commit d688e416)
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When starting a BLORP operation, we do the BTI-change flush. However, when ending it and transitioning back to regular drawing, we change the render target again - without a set_framebuffer_state() call. We need to do the BTI flush there too. BLORP flags IRIS_DIRTY_RENDER_BUFFER now, which will cause the next draw to get the BTI flush again. (explanation of fix by Ken) Fixes: 2b956a09 ("iris: totally untested icelake support") Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit bb0c5c48)
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Fixes: 2b956a09 ("iris: totally untested icelake support") Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit a2c3c65a)
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This make shader-db's report.py work on Haswell and earlier platforms. The problem is that the script would detect the "sends" output for scalar shaders and expect in in vec4 shaders too. When it didn't find it, the script would fail with: Traceback (most recent call last): File "./report.py", line 351, in <module> main() File "./report.py", line 182, in main before_count = before[p][m] KeyError: 'sends' Fixes: f192741d ("intel/compiler: Report the number of non-spill/fill SEND messages") Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 7b3f38ef)
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libdrm returns -errno instead of directly the ioctl ret of -1. Fixes: 1c3cda7d "radv: Add syncobj signal/reset/wait to winsys." Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit ec770085)
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Observed an issue when looking at the code generatedy by the image-vertex-attrib-input-output piglit test. Even though the test itself worked fine (due to TIC 0 being used for the image), this needs to be fixed. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 1b9d1e13)
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 8125d796 ("intel/dev: Add preliminary device info for Tigerlake") Acked-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit e02c181b)
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Unfortuantely we don't know if a particular load is a real 2d image (as would be a cube face or 2d array element), or a layer of a 3d image. Since we pass in the TIC reference, the instruction's type has to match what's in the TIC (experimentally). In order to properly support bindless images, this also can't be done by looking at the current bindings and generating appropriate code. As a result all plain 2d loads are converted into a pair of 2d/3d loads, with appropriate predicates to ensure only one of those actually executes, and the values are all merged in. This goes somewhat against the current flow, so for GM107 we do the OOB handling directly in the surface processing logic. Perhaps the other gens should do something similar, but that is left to another change. This fixes dEQP tests like image_load_store.3d.*_single_layer and GL-CTS tests like shader_image_load_store.non-layered_binding without breaking anything else. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "20.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 869e3259)
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- Oct 30, 2019
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Dylan Baker authored
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Jordan Justen authored
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
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Jordan Justen authored
These reworks were combined into this patch: * Matt Turner: i965: Disable NoDDChk/NoDDClr test on Gen12+ * Francisco Jerez: intel/eu/validate/gen12: Disable qword_low_power_no_depctrl eu_validate test. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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Jordan Justen authored
Reworks: * adjust 64-bit support, hiz (Jason Ekstrand) * sim-id (Lionel Landwerlin) * adjust threads, urb size (Rafael Antognolli) * adjust urb size (Kenneth Graunke) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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Lionel Landwerlin authored
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
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Bas Nieuwenhuizen authored
Calculated the number for allocation and did not reserve space .... Fixes: 2117c53b "radv: Add temporary datastructure for submissions." Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
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Rafael Antognolli authored
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