- Jun 06, 2024
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Eric Engestrom authored
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Eric Engestrom authored
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- May 31, 2024
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In order to turn on/off through SNMP DuT under PoE switch, the SNMP key in some vendors don't directly use the interface number, but a number shifted a base number. Define this base number as BM_POE_BASE environment in the runner. Reviewed-by:
Jose Maria Casanova Crespo <jmcasanova@igalia.com> Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com> Part-of: <mesa/mesa!29306> (cherry picked from commit 90f8be9b)
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Closes: mesa/mesa#11243 Cc: mesa-stable Part-of: <mesa/mesa!29483> (cherry picked from commit 6f713a76)
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Macro values that define values for different HW generations should use the V3DV_X helper instead of being defined under a V3D_VERSION #if condition. Without this change, the original V3D_CLE_READAHEAD and V3D_CLE_BUFFER_MIN_SIZE definitions used were only working for 4.2 HW. For the 7.1 HW (RPi5) the 4.2 definitions were applied. The CLE MMU errors were hidden as they were reported at dmesg as "MMU error from client PTB (1) at 0x1884200, pte invalid" instead of client CLE. So fixes all v3d dmesg warnings for PTB MMU errors on RPi5. With this change we really don't need different functions per HW generation, so we rename back file v3dx_cl.c to v3d_cl.c. As before, we can use only the packets definitions for 4.2 HW as they use the same opcode as 7.1 HW. Fixes: 11dce2ac ("v3d: fix CLE MMU errors avoiding using last bytes of CL BOs.") Fixes: e2c624e7 ("v3d: Increase alignment to 16k on CL BO on RPi5") Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!29496> (cherry picked from commit f32a2585)
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Macro values that define values for different HW generations should use the V3DV_X helper instead of being defined under a V3D_VERSION #if condition. Without this change, the original V3D_CLE_READAHEAD and V3D_CLE_BUFFER_MIN_SIZE definitions used were only working for 4.2 HW. For the 7.1 HW (RPi5) the 4.2 definitions were applied. The CLE MMU errors were hidden as they were reported at dmesg as "MMU error from client PTB (1) at 0x1884200, pte invalid" instead of client CLE. So fixes all v3dv dmesg warnings for PTB MMU errors on RPi5. With this change we really don't need different functions per HW generation, so we rename back file v3dvx_cl.c to v3dv_cl.c. As before, we can use only the packets definitions for 4.2 HW as they use the same opcode as 7.1 HW. It fixes also an indentation error introduced with 26c8a5cd. Fixes: bb77ac98 ("v3dv: Increase alignment to 16k on CL BO on RPi5") Fixes: 26c8a5cd ("v3dv: fix CLE MMU errors avoiding using last bytes of CL BOs.") Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!29496> (cherry picked from commit 07d3d557)
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Eric Engestrom authored
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Part-of: <mesa/mesa!29487> (cherry picked from commit fbb306df)
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Part-of: <mesa/mesa!29487> (cherry picked from commit 3ec48082)
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The SamplerDescriptor structure has a field which describes how floating point coordinates should be converted to fixed point. Setting this to "true" (which causes round to nearest even) fixes a failing CTS test. The CTS test in question is: dEQP-GLES31.functional.texture.border_clamp.range_clamp.linear_float_color The OpenGL spec is somewhat vague about how rounding is to be performed, so it appears both settings should be legal; this may indicate a problem with the CTS. Nevertheless "round to nearest even" is probably a better default and since it fixes the failing test we may as well use it. Cc: mesa-stable Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by:
Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!29464> (cherry picked from commit d91d2c27)
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Fixes compiling rusticl with certain configurations Cc: mesa-stable Signed-off-by:
Karol Herbst <kherbst@redhat.com> Acked-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Christian Gmeiner <cgmeiner@igalia.com> Part-of: <mesa/mesa!26680> (cherry picked from commit 691a22f0)
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This way frontends can simply link against the stub, but get the full version if it's actually required (e.g. for radeonsi). Cc: mesa-stable Signed-off-by:
Karol Herbst <kherbst@redhat.com> Acked-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Christian Gmeiner <cgmeiner@igalia.com> Part-of: <mesa/mesa!26680> (cherry picked from commit b6f281bc)
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Cc: mesa-stable Signed-off-by:
Karol Herbst <kherbst@redhat.com> Acked-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Christian Gmeiner <cgmeiner@igalia.com> Part-of: <mesa/mesa!26680> (cherry picked from commit 6c9c48a3)
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It's used by radeonsi Cc: mesa-stable Signed-off-by:
Karol Herbst <kherbst@redhat.com> Acked-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Christian Gmeiner <cgmeiner@igalia.com> Part-of: <mesa/mesa!26680> (cherry picked from commit 95871d48)
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We increased the size of the timestamps but only copied 64bit values from the secondaries. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 521c216e ("anv: use COMPUTE_WALKER post sync field to track compute work") Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!29438> (cherry picked from commit 1d4e56d2)
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The output of the POSTSYNC_DATA has to be 32-byte aligned. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 521c216e ("anv: use COMPUTE_WALKER post sync field to track compute work") Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!29438> (cherry picked from commit 1511b25b)
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Currently for an "unavailable" query, if VK_QUERY_RESULT_PARTIAL_BIT is set, anv will return (slot.end - slot.begin). This can cause underflow because slot.end might still be at the initial value of 0. This commit fixes the issue by returning 0 in that situation. Cc: mesa-stable Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!29447> (cherry picked from commit f8ccf70c)
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9b2780dc folds the kernel path into the compute path, and then adds a `compute -> compute` conversion that was very likely meant to be `kernel -> compute`, so fix that. Fixes: 9b2780dc ("freedreno/a6xx: Re-work fd6_emit_shader") Part-of: <mesa/mesa!29458> (cherry picked from commit b8f1e95c)
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Only GFX11 is affected by this hw bug. Found by inspection. Cc: mesa-stable Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!29424> (cherry picked from commit 07a826ba)
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The queueFlags of the associated queue may have more flags than just the type of queue it is, based on what that queue supports, like sparse or protected content. Check that the queue is a blitter engine instead. Fixes a bunch of dEQP-VK.api.copy_and_blit.core.*_transfer on MTL with ANV_SPARSE=0 Fixes: 17b8b2cf ("anv: Add support for a transfer queue on Alchemist") Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!29336> (cherry picked from commit 8d098ecf)
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The code for checking flow control did not realize that `LD_TEX` and `LD_TEX_IMM` were memory accesses, and hence was not inserting waits where these were necessary. This showed up as flakes in KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-fs Cc: mesa-stable Reviewed-by:
Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!29363> (cherry picked from commit 272dcaff)
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Fixes: 1e81bb05 (v3dv: implement workaround for GFXH-1461) Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!29427> (cherry picked from commit 4835dc0e)
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When programming the size, we should take into account the offset from the start of the index buffer address. cc: mesa-stable Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!29425> (cherry picked from commit 70aa470b)
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This layer was blocking Android emulated ASTC support as it did not take "emu_astc_ldr" in to account. Cc: mesa-stable Signed-off-by:
Tapani Pälli <tapani.palli@intel.com> Tested-by:
Mi, Yanfeng <yanfeng.mi@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!29415> (cherry picked from commit 6836118c)
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If we arent in a renderpass, but still wanna start the time elapsed query(eg. to figure out how long some random operation will take) then this seems to fix that case. Signed-off-by:
Yusuf Khan <yusisamerican@gmail.com> cc: mesa-stable Part-of: <mesa/mesa!29411> (cherry picked from commit 42ee8d80)
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This uses a lot of stack, which is apparently a problem for musl libc. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Cc: mesa-stable Part-of: <mesa/mesa!29379> (cherry picked from commit c9f5152d)
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Fixes: be4287c3 ("pipe: Extend get_feedback with additional metadata") Reviewed-by:
Sil Vilerino <sivileri@microsoft.com> Part-of: <mesa/mesa!29217> (cherry picked from commit cc03f2ea)
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In the sort functions used to sort varyings in gl_nir_link_varyings, we were only checking the first input for whether or not it is xfb. Check both inputs, and also provide a definite order for the xfb vs. non-xfb varyings (the xfb come last, as the initial sort established). This fixes a problem encountered on panfrost, where qsort could mix xfb and non-xfb varyings which started out separate. Note that the sort is still not stable. We probably should make it stable, but that is a more extensive change that's handled in a later commit. Cc: mesa-stable Signed-off-by:
Eric R. Smith <eric.smith@collabora.com> Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <mesa/mesa!29178> (cherry picked from commit 5102a922)
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Another architecture register that requires some care before reading. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 49ee3ae9 ("intel/compiler: Lower FIND_[LAST_]LIVE_CHANNEL in IR on Gfx8+") Tested-by:
Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!29319> (cherry picked from commit 2c65d90b)
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We can emit spill setup before RA if we use scratch. In that case we have the same situation as during spilling, with the caveat that we have already emitted the instructions so we need to find them (they should be the only instructions ones before the instructions accessing payload registers) and flag them as such. Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> cc: mesa-stable Part-of: <mesa/mesa!29343> (cherry picked from commit 865e682a)
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We read our payload registers first in the shader so we generally don't have to care about temps being allocated to them and stomping their value before we can read them. Hoewer, spilling setup instructions are an exception since these will be inserted first when there is any spilling in the program. To fix this, we flag RA nodes involved with these instructions so we can then try to avoid assiging these registers to them. Fixes CTS failures with V3D_DEBUG=opt_compile_time, particularly: dEQP-VK.binding_model.buffer_device_address.set0.depth2.basessbo.convertcheckuv2.nostore.single.std140.comp_offset_nonzero Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> cc: mesa-stable Part-of: <mesa/mesa!29343> (cherry picked from commit cb83f25b)
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Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> cc: mesa-stable Part-of: <mesa/mesa!29343> (cherry picked from commit 901c4859)
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Fixes: 94425716 ("ci: separate hiden jobs to -inc.yml files") Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!26758> (cherry picked from commit 6bc660a5)
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When compilation is required, we should return VK_PIPELINE_COMPILE_REQUIRED. The spec prevents the application from passing a module or SPIR-V code so we have nothing to compile if the cache lookup fails : VUID-VkPipelineShaderStageCreateInfo-stage-06844: If a shader module identifier is specified for this stage, a VkShaderModuleCreateInfo structure must not be present in the pNext chain VUID-VkPipelineShaderStageCreateInfo-stage-06848: If a shader module identifier is specified for this stage, module must be VK_NULL_HANDLE Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Closes: mesa/mesa#11208 Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!29340> (cherry picked from commit 5f228809)
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The GLES spec limits the valid combinations of format and type that may be returned by queries and/or used by ReadPixel. The list of valid combinations appears in table 8.2 of the GLES 3.2 spec. Our code for reporting the type and format of the current framebuffer, however, does not verify that the combination is legal for GLES. For example, RGBA and UNSIGNED_SHORT_1_5_5_5_REV is not a valid GLES combination, but it's what we were returning for a panthor 16 bit frame buffer. We can fix this either by changing the format or type that we return (internally we can handle any format/type combination). We advertise the read_format_bgra extension, so we could return GL_BGRA for the format. However, very few applications (including notably the Khronos CTS for GLES) cope well with BGRA. So instead we change the type to a non-_REV one so that the combination appears in the GLES spec table of legal values. Cc: mesa-stable Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <mesa/mesa!29144> (cherry picked from commit 4d298673)
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So that as soon as pipelines are freed, they're removed from the cache. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Closes: mesa/mesa#11185 Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Sagar Ghuge <sagar.ghuge@intel.com> Tested-by:
Brian Paul <brian.paul@broadcom.com> Reviewed-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Cc: mesa-stable Part-of: <mesa/mesa!29283> (cherry picked from commit 3584fc64)
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Eric Engestrom authored
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The gfx_level check was missing the version... Found by inspection. Fixes: 3f7ddaf2 ("radv: implement setting a custom pitch to any multiple of 256B on gfx10.3+" Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!29331> (cherry picked from commit 2867a079)
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As we are marking the last V3D_CLE_READAHEAD bytes as unusable we don't need to reserve V3D_CL_MAX_INSTR_SIZE bytes for the CLE packet. This reverts c2601f06 ("v3dv: ensure at least V3D_CL_MAX_INSTR_SIZE bytes in last CL instruction") Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> cc: mesa-stable Part-of: <mesa/mesa!29023> (cherry picked from commit 7afebc15)
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We increase the alignment to 16k for BOs allocated for the CL on RPi5 HW. So we have the same ratio of usable space because of HW readahead as than on RPi4, as readahead has been increased from 256 to 1024 bytes on RPi5. We have also concluded that when the kernel is running with 16k pages that is the default on Raspberry Pi 5 HW, BO allocations are aligned to 16k so this increase has no cost and we would be using memory more efficiently. Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> cc: mesa-stable Part-of: <mesa/mesa!29023> (cherry picked from commit bb77ac98)
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