- Mar 26, 2025
-
-
Alex Deucher authored
GC12 only has 1 mec. Fixes: 52cb80c1 ("drm/amdgpu: Add gfx v12_0 ip block support (v6)") Reviewed-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Alex Deucher authored
GC11 only has 1 mec. Fixes: 3d879e81 ("drm/amdgpu: add init support for GFX11 (v2)") Reviewed-by:
-
Asad Kamal authored
Add new gpu_metrics_v1_8 to acquire below host limit counters Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
-
lijo lazar authored
Fetch VBIOS from shadow ROM when available before trying other methods like EFI method. Signed-off-by:
-
Asad Kamal authored
Update smu metrics table to vesrion 0x10 for smu_v13_0_6 v2: Host metrics support removal moved to separate patch (Lijo) Signed-off-by:
-
Asad Kamal authored
Firmware algorithm changed and the values in this version are not accurate thereby remove host limit metric support for smu_v13_0_6, smu_v13_0_12 & smu_v13_0_14 Signed-off-by:
-
Candice Li authored
GC v9_4_2 uses a new versioning scheme for CP firmware, making the warning ("CP firmware version too old, please update!") irrelevant. Signed-off-by:Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Christian König authored
This looks unnecessary and actually extremely harmful since using kmap() is not possible while inside the ring reset. Remove all the extra mapping and unmapping of the MQDs. v2: also fix debugfs v3: fix coding style typo Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
-
Jie1zhang authored
this temporarily reverts commit 6ec04e38 ("drm/amdgpu/sdma_v4_4_2: update VM flush implementation for SDMA") it cause a regression. Signed-off-by:
Jesse Zhang <jesse.zhang@amd.com> Reviewed-by:
-
Xiang Liu authored
We should only increase the deferred errors in UMC block. Signed-off-by:
Xiang Liu <xiang.liu@amd.com> Reviewed-by:
-
stanley yang authored
Update ta ra block to keep sync with RAS TA. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
-
lijo lazar authored
Compute partition DPX is possible in NPS2 mode. Update the compatible modes for DPX. Signed-off-by:
-
Xiang Liu authored
In the case of parsing GFX deferred error from SMU corrected error channel, the error count should be set to 1 instead of parsing from MISC0 register, which is 0. Signed-off-by:
-
Leo Li authored[Why] The `vblank_config.offdelay` field follows the same semantics as the `drm_vblank_offdelay` parameter. Setting it to 0 will never disable vblank. [How] Set `offdelay` to a positive number. Fixes: e45b6716 ("drm/amd/display: use a more lax vblank enable policy for DCN35+") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Leo Li <sunpeng.li@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
-
Brendan Tam authored
[Why] When link training fails, the phy clock will be disabled. However, in enable_streams, it is assumed that link training succeeded and the mux selects the phy clock, causing a hang when a register write is made. [How] When enable_stream is hit, check if link training failed. If it did, fall back to the ref clock to avoid a hang and keep the system in a recoverable state. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
Brendan Tam <Brendan.Tam@amd.com> Signed-off-by:
-
Charlene Liu authored
[why] this dscclk use DCN defined per DPM level will cause a DCFCLK increase. needs to follow up. This reverts commit 15b95953 Reviewed-by:
Yihan Zhu <yihan.zhu@amd.com> Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Signed-off-by:
-
Leo Li authored
[Why] Depending on when the HW latching event (vupdate) of double-buffered registers happen relative to the PSR SDP (signals panel psr enter/exit) deadline, and how bad the Panel clock has drifted since the last ALPM off event, there can be up to 3 frames of delay between sending the PSR exit cmd to DMUB fw, and when the panel starts displaying live frames. This can manifest as micro-stuttering when userspace commit patterns cause rapid toggling of the DRM vblank counter, since PSR enter/exit is hooked up to DRM vblank disable/enable respectively. In the ideal world, the panel should present the live frame immediately on PSR exit cmd. But due to HW design and PSR limitations, immediate exit can only happen by chance, when: 1. PSR exit cmd is ack'd by FW before HW latching (vupdate) event, and 2. Panel's SDP deadline -- determined by it's PSR Start Delay in DPCD 71h -- is after the vupdate event. The PSR exit SDP can then be sent immediately after HW latches. Otherwise, we have to wait 1 frame. And 3. There is negligible drift between the panel's clock and source clock. Otherwise, there can be up to 1 frame of drift. Note that this delay is not expected with Panel Replay. [How] Since PSR power savings can be quite substantial, and there are a lot of systems in the wild with PSR panels, It'll be nice to have a middle ground that balances user experience with power savings. A simple way to achieve this is by extending the vblank offdelay, such that additional PSR exit delays will be less perceivable. We can set: 20/100 * offdelay_ms = 3_frames_ms => offdelay_ms = 5 * 3_frames_ms This ensures that `3_frames_ms` will only be experienced as a 20% delay on top how long the panel has been static, and thus make the delay less perceivable. If this ends up being too high of a percentage, it can be dropped further in a future change. Fixes: 537ef0f8 ("drm/amd/display: use new vblank enable policy for DCN35+") Reviewed-by:
Leo Li <sunpeng.li@amd.com>
Signed-off-by: -
Mario Limonciello authored
If compiled without SI or CIK support but amdgpu tries to load it will run into failures with uninitialized callbacks. Show a nicer message in this case and fail probe instead. Closes: drm/amd#4050 Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
-
Tomasz Pakuła authoredHook up zero RPM enable for 9070 and 9070 XT based on RDNA3 (smu 13.0.0 and 13.0.7) code. Tested on 9070 XT Hellhound Signed-off-by:
Tomasz Pakuła <tomasz.pakula.oficjalny@gmail.com> Signed-off-by:
-
Denis Arefev authored
The user can set any speed value. If speed is greater than UINT_MAX/8, division by zero is possible. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: c52dcf49 ("drm/amd/pp: Avoid divide-by-zero in fan_ctrl_set_fan_speed_rpm") Signed-off-by:
Denis Arefev <arefev@swemel.ru> Signed-off-by:
-
Denis Arefev authored
The user can set any speed value. If speed is greater than UINT_MAX/8, division by zero is possible. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: c52dcf49 ("drm/amd/pp: Avoid divide-by-zero in fan_ctrl_set_fan_speed_rpm") Signed-off-by:
-
Denis Arefev authored
The user can set any speed value. If speed is greater than UINT_MAX/8, division by zero is possible. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 031db090 ("drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2") Signed-off-by:
-
Denis Arefev authored
The user can set any speed value. If speed is greater than UINT_MAX/8, division by zero is possible. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: b64625a3 ("drm/amd/pm: correct the address of Arcturus fan related registers") Signed-off-by:
-
Denis Arefev authored
The user can set any speed value. If speed is greater than UINT_MAX/8, division by zero is possible. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: c05d1c40 ("drm/amd/swsmu: add aldebaran smu13 ip support (v3)") Signed-off-by:
-
- Mar 24, 2025
-
-
Dave Airlie authored
Merge tag 'drm-intel-gt-next-2025-03-12' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next UAPI Changes: - Increase I915_PARAM_MMAP_GTT_VERSION version to indicate support for partial mmaps (José Roberto de Souza) Driver Changes: Fixes/improvements/new stuff: - Implement vmap/vunmap GEM object functions (Asbjørn Sloth Tønnesen) Miscellaneous: - Various register definition cleanups (Ville Syrjälä) - Fix typo in a comment [gt/uc] (Yuichiro Tsuji) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Tvrtko Ursulin <tursulin@igalia.com> Link: https://patchwork.freedesktop.org/patch/msgid/Z9IXs5CzHHKScuQn@linux
-
Dave Airlie authored
Merge tag 'amd-drm-next-6.15-2025-03-21' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.15-2025-03-21: amdgpu: - Refine nomodeset handling - RAS fixes - DCN 3.x fixes - DMUB fixes - eDP fixes - SMU 14.0.2 fixes - SMU 13.0.6 fixes - SMU 13.0.12 fixes - SDMA engine reset fixes - Enforce Isolation fixes - Runtime workload profile ref count fixes - Documentation fixes - SR-IOV fixes - MES fixes - GC 11.5 cleaner shader support - SDMA VM invalidation fixes - IP discovery improvements for GC based chips amdkfd: - Dequeue wait count fixes - Precise memops fixes radeon: - Code cleanup Signed-off-by:
-
Dave Airlie authored
Merge tag 'amd-drm-next-6.15-2025-03-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.15-2025-03-14: amdgpu: - GC 12.x DCC fixes - VCN 2.5 fix - Replay/PSR fixes - HPD fixes - DMUB fixes - Backlight fixes - DM suspend/resume cleanup - Misc DC fixes - HDCP UAF fix - Misc code cleanups - VCE 2.x fix - Wedged event support - GC 12.x PTE fixes - Misc multimedia cap fixes - Enable unique id support for GC 12.x - XGMI code cleanup - GC 11.x and 12.x MQD cleanups - SMU 13.x updates - SMU 14.x fan speed reporting - Enable VCN activity reporting for additional chips - SR-IOV fixes - RAS fixes - MES fixes amdkfd: - Dequeue wait count API cleanups - Queue eviction cleanup fixes - Retry fault fixes - Dequeue retry timeout adjustments - GC 12.x trap handler fixes - GC 9.5.x updates radeon: - VCE command parser fix Signed-off-by:
-
Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2025-03-13' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next Short summary of fixes pull: appletbdrm: - Fix device refcount Signed-off-by:
-
- Mar 21, 2025
-
-
Asad Kamal authored
Update feature list for smu_v13_0_6 to show vcn & smu deep sleep feature enable status Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
-
SRINIVASAN SHANMUGAM authored
The 'flags' parameter, which specifies memory allocation behavior while creating a sync entry, Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:162: warning: Function parameter or struct member 'flags' not described in 'amdgpu_sync_fence' Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
-
Alex Deucher authored
On chips without native IP discovery support, use the fw binary if available, otherwise we can continue without it. Signed-off-by:
Flora Cui <flora.cui@amd.com> Signed-off-by:
-
fcui authored
vega10/vega12/vega20/raven/raven2/picasso/arcturus/aldebaran Signed-off-by:
-
fcui authored
Signed-off-by:
-
Asad Kamal authored
Few of the metrics data for smu_v13_0_12 has not been reported in Q10 format, remove UQ10 to UINT conversion for those Signed-off-by:
-
Asad Kamal authored
Few of the metrics data for smu_v13_0_6 has not been reported in Q10 format, remove UQ10 to UINT conversion for those v2: Move smu_v13_0_12 changes to separate patch(Kevin) Signed-off-by:
-
Jie1zhang authored
This commit updates the VM flush implementation for the SDMA engine. - Added a new function `sdma_v4_4_2_get_invalidate_req` to construct the VM_INVALIDATE_ENG0_REQ register value for the specified VMID and flush type. This function ensures that all relevant page table cache levels (L1 PTEs, L2 PTEs, and L2 PDEs) are invalidated. - Modified the `sdma_v4_4_2_ring_emit_vm_flush` function to use the new `sdma_v4_4_2_get_invalidate_req` function. The updated function emits the necessary register writes and waits to perform a VM flush for the specified VMID. It updates the PTB address registers and issues a VM invalidation request using the specified VM invalidation engine. - Included the necessary header file `gc/gc_9_0_sh_mask.h` to provide access to the required register definitions. v2: vm flush by the vm inalidation packet (Lijo) v3: code stle and define thh macro for the vm invalidation packet (Christian) v4: Format definition sdma vm invalidate packet (Lijo) Suggested-by:
-
Jie1zhang authored
- Modify the VM invalidation engine allocation logic to handle SDMA page rings. SDMA page rings now share the VM invalidation engine with SDMA gfx rings instead of allocating a separate engine. This change ensures efficient resource management and avoids the issue of insufficient VM invalidation engines. - Add synchronization for GPU TLB flush operations in gmc_v9_0.c. Use spin_lock and spin_unlock to ensure thread safety and prevent race conditions during TLB flush operations. This improves the stability and reliability of the driver, especially in multi-threaded environments. v2: replace the sdma ring check with a function `amdgpu_sdma_is_page_queue` to check if a ring is an SDMA page queue.(Lijo) v3: Add GC version check, only enabled on GC9.4.3/9.4.4/9.5.0 v4: Fix code style and add more detailed description (Christian) v5: Remove dependency on vm_inv_eng loop order, explicitly lookup shared inv_eng(Christian/Lijo) v6: Added search shared ring function amdgpu_sdma_get_shared_ring (Lijo) Suggested-by:
-
Jie1zhang authored
Increase the maximum number of rings supported by the AMDGPU driver from 133 to 149. This change is necessary to enable support for the SDMA page ring. Signed-off-by:
-
Xiang Liu authored
In the case of injecting uncorrected error with background workload, the deferred error among uncorrected errors need to be specified by checking the deferred and poison bits of status register. v2: refine checking for deferred error v2: log possiable DEs among CEs v2: generate CPER records for DEs among UEs Signed-off-by:
-
SRINIVASAN SHANMUGAM authored
Enable the cleaner shader for GFX11.5.0/11.5.1 GPUs to provide data isolation between GPU workloads. The cleaner shader is responsible for clearing the Local Data Store (LDS), Vector General Purpose Registers (VGPRs), and Scalar General Purpose Registers (SGPRs), which helps prevent data leakage and ensures accurate computation results. This update extends cleaner shader support to GFX11.5.0/11.5.1 GPUs, previously available for GFX11.0.3. It enhances security by clearing GPU memory between processes and maintains a consistent GPU state across KGD and KFD workloads. Cc: Mario Sopena-Novales <mario.novales@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
-
