- Jan 13, 2021
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Dylan Baker authored
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Samuel Pitoiset authored
It should work fine now. This gives +1-2% improvements with Control MSAA (2x and 4x) on Sienna. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8413>
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Boris Brezillon authored
The base offset was ignored, take it into account. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!8469>
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Ilia Mirkin authored
Otherwise the delete yells at us that there's still work pending. This isn't an actual problem, but annoying to see each time. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!8462>
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Timur Kristóf authored
This is a copy of the expected failures list of Pitcairn (also GFX6) with some Oland specific failures added. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!8473>
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Thong Thai authored
Add a check to vaDeriveImage to see if a non-interlaced buffer was created successfully. Otherwise, return an error, since we won't be able to derive an image from the interlaced buffer. Prevents a null pointer dereference from occuring on some nVidia cards, reported by Alexander Kapshuk. v2: Check for PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE support (Ilia) Fixes: fcb55832 ("frontends/va: Derive image from interlaced buffers") Signed-off-by: Thong Thai <thong.thai@amd.com> Tested-by: Alexander Kapshuk <alexander.kapshuk@gmail.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Part-of: <mesa/mesa!8320>
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Bas Nieuwenhuizen authored
Especially on GFX10 we can avoid pretty much all L2 flushes. However, instead of that we have to do L2_METADATA invalidations. We do that every time we could possibly be reading new DCC/HTILE info from the L2 cache in shaders. Benchmark results, basemark on high preset with a navi10 on profile_standard (which is slower than a navi10 on default settings, please don't compare to random navi10 results you find) before: 5932 5928 5937 after: 6011 6013 6009 So this looks like a >1% increase. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!7202>
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Bas Nieuwenhuizen authored
This enables assuming that the L2 is always up to date for barriers. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!7202>
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Bas Nieuwenhuizen authored
This way we're properly using the vulkan barrier paradigm instead of adhoc guessing what caches need to be flushed. This is more robust for cache policy changes as we now don't have to revisit all the meta operations all the time. Note that a barrier has both a src and dst part though. So barrier: flush src meta op flush dst becomes barrier: flush barrier src flush meta op dst meta op flush meta op src flush barrier dst And there are some places where we've been able to replace a CB flush with a shader flush because that is what we'd need according to vulkan rules (and it turns out that in the cases the CB flush mattered the app will set the bit in one of the relevant flushes or it was needed as a result of an optimization that we counter-acted in the previous patch.) Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!7202>
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Bas Nieuwenhuizen authored
For write-after-write hazards. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!7202>
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Bas Nieuwenhuizen authored
To cancel the optimization in radv_dst_access_flush if these helpers get used by meta operations. We could also remove that optimization but I think this triggers less often as all SHADER_WRITE flushes on images not supporting STORAGE should be meta Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!7202>
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Bas Nieuwenhuizen authored
INV_L2 already does that. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!7202>
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Alyssa Rosenzweig authored
On Midgard, we still have to lower on v6+. Passes Piglit ./fbo-mrt-alphatest (saving a cycle in the fragment shader to compare/discard). Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!8447>
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Alyssa Rosenzweig authored
Midgard only, v6 dropped support. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!8447>
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Alyssa Rosenzweig authored
Don't fall back. Passes piglit ./bin/primitive-restart on Bifrost. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!8447>
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Samuel Pitoiset authored
I attempted to enable it for 21.0, only 2x and 4x were supported but there is new failures if DCC+MSAA is enabled. Disable it again because DCC is more important than this feature and no Mesa releases have it on GFX10+. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8472>
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Boris Brezillon authored
This function returns true for PIPE_FORMAT_R8G8B8X8_UNORM, which is wrong. Fixes: 44217be9 ("panfrost: Adjust the format for AFBC textures on Bifrost v7") Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <mesa/mesa!8466>
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Samuel Pitoiset authored
Seems to work fine. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8468>
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Samuel Pitoiset authored
This is broken for some reasons, and probably rare enough to care for now. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8468>
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Samuel Pitoiset authored
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8468>
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Samuel Pitoiset authored
When size is 0, this means the level can't be compressed. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8468>
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Samuel Pitoiset authored
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8468>
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Alyssa Rosenzweig authored
Saves a few instructions in the common case. Requires refactoring the TEXS check. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!8287>
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Rhys Perry authored
The argument evaluation order is implementation-defined and affects the order the instructions are inserted. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de> Closes: mesa/mesa#3938 Part-of: <mesa/mesa!7945>
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Juan A. Suárez authored
This extends the TLB based blit to support both depth and stencil buffers. v2: - Ammend comment for further clarification (Iago) - Remove parenthesis (Iago) - Remove condition so separate stencil blit is done (Iago) Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!8304>
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Juan A. Suárez authored
Move the blit mask check (RGBA, Depth/Stencil) inside the blit paths (stencil, TFU, TLB and render blit paths). v2: - Add missing Fixes tag (Iago) Fixes: 1c76f6e7 ("v3d: implement tile-based blit operation") Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!8304>
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Samuel Pitoiset authored
If we have CMASK, we can also skip FCE like we do for DCC. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8332>
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Samuel Pitoiset authored
Fast clearing with CMASK should always be eliminated. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8332>
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Samuel Pitoiset authored
In case we don't have DCC, we can still predicate FCE with CMASK. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8332>
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Samuel Pitoiset authored
The FCE predicate value is only allocated if DCC is enabled. We only want to use predication for DCC decompressions and for FCE but not having FMASK doesn't mean the predicate is allocated. Closes: mesa/mesa#4075 Fixes: 6e7008e9 ("radv: do not predicate FMASK decompression when DCC+MSAA is used") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8441>
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Danylo Piliaiev authored
Vulkan guarantees only 4 byte alignment of offset for vkCmdDrawIndirect, while CP_LOAD_STATE.EXT_SRC_ADDR requires 16 byte alignment which makes us copy indirect parameters to a correctly aligned buffer. Blob does essentially the same but emits indirect CP_LOAD_STATE with src = SS6_UBO and EXT_SRC_ADDR = 0xe0000, and only for a first dispatch. Fixes: dEQP-VK.compute.indirect_dispatch.* Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <mesa/mesa!8444>
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Danylo Piliaiev authored
In Turnip local group size is lowered in NIR via nir_lower_compute_system_values. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <mesa/mesa!8444>
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Pierre-Eric Pelloux-Prayer authored
If reading from an FBO that uses a texture view src->format will be the format of the original texture, not from the view. Acked-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!8387>
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Pierre-Eric Pelloux-Prayer authored
Otherwise this resets is_rtt to false in st/mesa, and then breaks fbo + texture view. This change also aligns the code with the comment above: * Note that if the ReadBuffer has texture attachments we don't consider * that a render-to-texture case. Acked-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!8387>
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Pierre-Eric Pelloux-Prayer authored
Closes: mesa/mesa#4034 Acked-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!8387>
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Gert Wollny authored
In release builds the assert goes away resulting in build failures because no return value was specified. Fixes 165fb511 r600/sfn: add lowering passes to get 64 bit ops lowered to 32 bit vec2 Closes #4089 Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <mesa/mesa!8465>
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Samuel Pitoiset authored
dcc_slice_size is in DWORD on GFX9... Also, layers aren't supported because they might be interleaved. Fix this by clearing the entire DCC buffer. Fixes: 5e8f6967 ("radv: add support for fast-clearing DCC layers on GFX9+") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!8443>
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Christian Gmeiner authored
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!8438>
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Christian Gmeiner authored
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!8438>
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Christian Gmeiner authored
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!8438>
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