- Dec 29, 2021
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Eric Engestrom authored
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Eric Engestrom authored
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Fixes: 55d80228 "radv: Add winsys functions for timeline syncobj." Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!14165> (cherry picked from commit 20b51cda)
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1. the dst stride may be too small if count=1. 2. the src stride may be too small due to the availability bit. So lets just compute the size needed explicitly and use it. Fixes: 90a0556c ("radv: use pool stride when copying single query results") Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!14242> (cherry picked from commit afff9dd0)
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Uplay needs this to avoid a crash because it does an use-after-free of a descriptor set layout. This was initially introduced by Bas to workaround a similar issue with Baldur's Gate 3, it seems needed again. Cc: 21.3 mesa-stable Closes: mesa/mesa#5789 Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!14318> (cherry picked from commit b775aaff)
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We tried to step over the instruction we just generated, except we didn't always just generate one. In the sequence_vertex tests, that meant we skipped processing the next BGNLOOP and then underflowed our stack. Cc: mesa-stable Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!14271> (cherry picked from commit 658b2ca4)
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This is a quick hack for a bunch of the fail in #5766. Cc: mesa-stable Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!14271> (cherry picked from commit e41a53cd)
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It's buggy, and we should just trust GLSL or NIR to do unrolling for us. Cc: mesa-stable Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!14096> (cherry picked from commit e68a9b03)
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Since we typically use an ALU op to set the condition modifier for the IF-BRK-ENDIF, we were particularly likely to remove the increment of the loop counter! Cc: mesa-stable Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!14117> (cherry picked from commit 26b3e2f7)
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We only have one bit of negate, so we have to make sure that immediate usage has matching negates on all used channels (or rewrite to do so). Cc: mesa-stable Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!14117> (cherry picked from commit d6fed4ab)
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rc_get_variables() is slow, don't call it if we're going to just exit immediately anyway. Cc: mesa-stable Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!14117> (cherry picked from commit 42e8f48b)
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Cc: mesa-stable Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!14092> (cherry picked from commit 65e343dd)
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Fixes: cb283616 ("nir/algebraic: Small optimizations for SpvOpFOrdNotEqual and SpvOpFUnordEqual") Reviewed-by:
Enrico Galli <enrico.galli@intel.com> Reviewed-by:
Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!14140> (cherry picked from commit 45354be4)
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Fixes: e002f5a0 ("gallium: change pipe_vertex_element::src_format to uint8_t") Closes: #5550 Authored-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!13908>
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I noticed that GLSL version referenced here was wrong, version 4.20 is first spec that does not allow invariant keyword for inputs. v2: fix all comments (Timothy Arceri) Fixes: f9f46293 ("glsl: Fix invariant matching in GLSL 4.30 and GLSL ES 1.00.") Signed-off-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Timothy Arceri <tarceri@itsqueeze.com> Part-of: <mesa/mesa!14241> (cherry picked from commit ebd1f202)
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Fix defect reported by Coverity Scan. Double unlock (LOCK) double_unlock: pthread_mutex_unlock unlocks dev->indirect_draw_shaders.lock while it is unlocked. Fixes: 2e6d94c1 ("panfrost: Add helpers to support indirect draws") Suggested-by:
Alyssa Rosenzweig <alyssa@collabora.com> Signed-off-by:
Vinson Lee <vlee@freedesktop.org> Part-of: <!14262> (cherry picked from commit 9f8a2046)
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Fixes: a93092d0 Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <mesa/mesa!14281> (cherry picked from commit b2932997)
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Fixes: 4ac47ad1 Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <mesa/mesa!14281> (cherry picked from commit ce4daa25)
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We have to clear the register file from the previous operand as otherwise, there might be no space left. Totals from 5 (0.00% of 134572) affected shaders: (GFX10.3) CodeSize: 21144 -> 21000 (-0.68%); split: -0.72%, +0.04% Instrs: 3738 -> 3720 (-0.48%); split: -0.51%, +0.03% Latency: 517229 -> 516319 (-0.18%); split: -0.18%, +0.00% InvThroughput: 49068 -> 48902 (-0.34%); split: -0.38%, +0.04% Copies: 501 -> 483 (-3.59%); split: -3.79%, +0.20% Cc: mesa-stable Reviewed-by:
Timur Kristóf <timur.kristof@gmail.com> Part-of: <mesa/mesa!14279> (cherry picked from commit d36a4359)
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Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Cc: mesa-stable Part-of: <mesa/mesa!13688> (cherry picked from commit 193bd740)
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This adds a missing CFG edge that represents a possible physical control flow path the EU might take under some conditions which isn't part of the logical CFG of the program. This possibility shouldn't have led to problems on platforms prior to Gfx12, since the missing control flow edge cannot possibly influence liveness intervals. However on Gfx12+ it becomes the compiler's responsibility to resolve data dependencies across instructions, and the missing physical control flow paths may lead to a WaR data hazard currently not visible to the software scoreboard pass, which could lead to data corruption. Worse, the possibility for this path to be taken by the EU increases on Gfx12+ due to a hardware bug affecting EU fusion -- However the same physical path can be potentially taken on earlier platforms as well, so this patch extends the CFG on all platforms for consistency, even though the lack of this edge shouldn't lead to any functional issues on platforms earlier than Gfx12. There are no shader-db changes on earlier platforms, so there seems to be no disadvantage from using the same CFG representation as on later platforms. This issue has ben reported on TGL with the following conformance test, thanks to Ian for bringing the FULSIM dependency check warning to my attention: dEQP-VK.graphicsfuzz.spv-stable-pillars-volatile-nontemporal-store Fixes: 4d1959e6 ("intel/cfg: Represent divergent control flow paths caused by non-uniform loop execution.") Closes: mesa/mesa#4940 Reported-by:
Tapani Pälli <tapani.palli@intel.com> Reported-by:
Ian Romanick <ian.d.romanick@intel.com> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!14248> (cherry picked from commit e7470a40)
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Order is important in the grammar, the more specific match needs to go first. Fixes: ba1c9893 ("freedreno/computerator: pass iova of buffer to const register") Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!14231> (cherry picked from commit d1edc6d9)
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Without this, a cloned instruction that takes full regs will trigger an ir3_validate assert. This can happen, for ex, if an instruction that writes p0.x and has a relative src gets cloned in ir3_sched. Fixes an assert in Genshin Impact with a debug build. Fixes: 9af795d9 ("ir3: Make ir3_instruction::address a normal register") Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!14231> (cherry picked from commit 78c53f48)
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Off-by-one on the start. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com> Reported-by:
Icecream95 <ixn@disroot.org> Fixes: 73e80994 ("panfrost: Add secondary shader XML fields") Part-of: <mesa/mesa!14154> (cherry picked from commit 8dc1936f)
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There should never be a CPU pointer in GPU memory, let's say that... Fixes: 2e6d94c1 ("panfrost: Add helpers to support indirect draws") Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!14154> (cherry picked from commit d696183d)
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We already have code to deal with non-client-visible objects but we were asserting if it didn't fall into one of the clearly mappable error cases. However, we didn't have a mapping for VK_ERROR_NOT_PERMITTED which can happen during object creation. Let's just be sloppy and drop the assert. Worst case, the client gets an error with no object. Reviewed-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> Part-of: <mesa/mesa!13341> (cherry picked from commit 116e23e3)
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Eric Engestrom authored
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Eric Engestrom authored
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- Dec 17, 2021
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Eric Engestrom authored
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Eric Engestrom authored
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This function is called on load/store_input/output. It makes no sense for it to get a SYSTEM_VALUE enum. This only doesn't explode because SYSTEM_VALUE_PRIMITIVE_ID happens to be below VARYING_SLOT_VAR0 so it doesn't interact with any actual varyings. The next commit is going to add another system value which will push SYSTEM_VALUE_PRIMITIVE_ID up by one so it will equal VARYING_SLOT_VAR0 and then the first FS input will always get smashed to flat which isn't what we want. Fixes: b59bb9c0 ("radeonsi: force flat for PrimID early in si_nir_scan_shader") Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!14198> (cherry picked from commit 732b234d)
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: b996fa8e ("anv: implement VK_KHR_synchronization2") Closes: mesa/mesa#5744 Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!14237> (cherry picked from commit cdf10145)
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src/intel/tools/intel_noop_drm_shim.c:459:36: warning: initialized field overwritten [-Woverride-init] 459 | [DRM_I915_GEM_EXECBUFFER2_WR] = i915_ioctl_noop, | ^~~~~~~~~~~~~~~ Fixes: 0f4f1d70 ("intel: add stub_gpu tool") Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!14218> (cherry picked from commit 2dc7c24b)
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Fixes: 22673a98 ("meson: Check arguments before adding") Reviewed-by:
Emma Anholt <emma@anholt.net> Part-of: <!13961> (cherry picked from commit 631b3fe3)
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Fixes: c7fc44f9 ("nir/from_ssa: Respect and populate divergence information") Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!14205> (cherry picked from commit dcc7b19c)
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I copied stuff from ac_gpu_info.c until there were no Sienna Cichild or Polaris10 fossil-db changes between real hardware and RADV_FORCE_FAMILY. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Cc: mesa-stable Part-of: <mesa/mesa!14126> (cherry picked from commit 451e6c1b)
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Fixes: 55be94dc ("iris/bufmgr: Add new set of buckets for local memory.") Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!14012> (cherry picked from commit f93892c5)
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Insert a flush after a depth decompression pass if the texture was fast cleared. This fixes a corruption which seems to only affect gfx10.3 chips. Ideally we should also clear tex->need_flush_after_depth_decompression after a flush but there's no easy way for this so this commit will introduce extra flushes. Cc: mesa-stable Part-of: <mesa/mesa!14089> (cherry picked from commit 573d6451)
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Currently V3DV_HAS_SURFACE is always defined. There is no WSI for Android in mesa3d, therefore WSI related extensions should not be exposed. 1. Define V3DV_HAS_SURFACE only for platforms which has WSI implemented. 2. Rename V3DV_HAS_SURFACE -> V3DV_USE_WSI_PLATFORM to align naming with other platforms. Fixes dEQP-VK.wsi.android.surface#query_protected_capabilities Fixes: 79e44514 ("v3dv: move extensions table to v3dv_device") Signed-off-by:
Roman Stratiienko <roman.o.stratiienko@globallogic.com> Reviewed-by:
Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <mesa/mesa!14144> (cherry picked from commit fcfc4ddf)
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This might have led to a leak in firefox/webrender/webgl scenarios Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> Fixes: f3630548 ("crocus: initial gallium driver for Intel gfx 4-7") Part-of: <mesa/mesa!14167> (cherry picked from commit 76da4569)
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