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Commit 9574e5de authored by Lionel Landwerlin's avatar Lionel Landwerlin Committed by unerlige
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lib/i915/perf: expose new operators for codegen


Newer platform started to use operators we didn't implement.

Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: default avatarUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
parent c58e3fa1
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......@@ -150,11 +150,17 @@ class Gen:
self.ops["<<"] = (2, self.emit_lshft)
self.ops[">>"] = (2, self.emit_rshft)
self.ops["AND"] = (2, self.emit_and)
self.ops["UGTE"] = (2, self.emit_ugte)
self.ops["UGT"] = (2, self.emit_ugt)
self.ops["ULTE"] = (2, self.emit_ulte)
self.ops["ULT"] = (2, self.emit_ult)
self.exp_ops = {}
# (n operands, splicer)
self.exp_ops["AND"] = (2, self.splice_bitwise_and)
self.exp_ops["UGTE"] = (2, self.splice_ugte)
self.exp_ops["UGT"] = (2, self.splice_ugt)
self.exp_ops["ULTE"] = (2, self.splice_ulte)
self.exp_ops["ULT"] = (2, self.splice_ult)
self.exp_ops["&&"] = (2, self.splice_logical_and)
......@@ -238,6 +244,22 @@ class Gen:
self.c("uint64_t tmp{0} = {1} & {2};".format(tmp_id, args[1], args[0]))
return tmp_id + 1
def emit_ulte(self, tmp_id, args):
self.c("uint64_t tmp{0} = {1} <= {2};".format(tmp_id, args[1], args[0]))
return tmp_id + 1
def emit_ult(self, tmp_id, args):
self.c("uint64_t tmp{0} = {1} < {2};".format(tmp_id, args[1], args[0]))
return tmp_id + 1
def emit_ugte(self, tmp_id, args):
self.c("uint64_t tmp{0} = {1} >= {2};".format(tmp_id, args[1], args[0]))
return tmp_id + 1
def emit_ugt(self, tmp_id, args):
self.c("uint64_t tmp{0} = {1} > {2};".format(tmp_id, args[1], args[0]))
return tmp_id + 1
def brkt(self, subexp):
if " " in subexp:
return "(" + subexp + ")"
......@@ -250,12 +272,18 @@ class Gen:
def splice_logical_and(self, args):
return self.brkt(args[1]) + " && " + self.brkt(args[0])
def splice_ulte(self, args):
return self.brkt(args[1]) + " <= " + self.brkt(args[0])
def splice_ult(self, args):
return self.brkt(args[1]) + " < " + self.brkt(args[0])
def splice_ugte(self, args):
return self.brkt(args[1]) + " >= " + self.brkt(args[0])
def splice_ugt(self, args):
return self.brkt(args[1]) + " > " + self.brkt(args[0])
def resolve_variable(self, name, set):
if name in self.hw_vars:
return self.hw_vars[name]['c']
......
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