- Jul 26, 2022
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Vulkan would like to have a rough measure of how much device memory can in theory be allocated. Also add unallocated_cpu_visible_size to track the visible portion, in case the device is using small BAR. Also tweak the locking so we nice consistent values for both the mm->avail and the visible tracking. v2: tweak the locking slightly so we update the mm->avail and visible tracking as one atomic operation, such that userspace doesn't get strange values when sampling the values. Testcase: igt@i915_query@query-regions-unallocated Testcase: igt@i915_query@query-regions-sanity-check Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Kenneth Graunke <kenneth@whitecape.org> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Reviewed-by:
Thomas Hellström <thomas.hellstrom@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220629174350.384910-3-matthew.auld@intel.com
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Userspace wants to know the size of CPU visible portion of device local-memory, and on small BAR devices the probed_size is no longer enough. In Vulkan, for example, it would like to know the size in bytes for CPU visible VkMemoryHeap. We already track the io_size for each region, so plumb that through to the region query. v2: Drop the ( -1 = unknown ) stuff, which is confusing since nothing can currently ever return such a value. Testcase: igt@i915_query@query-regions-sanity-check Signed-off-by:
Nirmoy Das <nirmoy.das@intel.com> Reviewed-by:
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Add an entry for the new uapi needed for small BAR on DG2+. v2: - Some spelling fixes and other small tweaks. (Akeem & Thomas) - Rework error capture interactions, including no longer needing NEEDS_CPU_ACCESS for objects marked for capture. (Thomas) - Add probed_cpu_visible_size. (Lionel) v3: - Drop the vma query for now. - Add unallocated_cpu_visible_size as part of the region query. - Improve the docs some more, including documenting the expected behaviour on older kernels, since this came up in some offline discussion. v4: - Various improvements all over. (Tvrtko) v5: - Include newer integrated platforms when applying the non-recoverable context and error capture restriction. (Thomas) Mesa: mesa/mesa!16739 Signed-off-by:Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Acked-by:
Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by:
Jordan Justen <jordan.l.justen@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220629174350.384910-1-matthew.auld@intel.com
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The only difference between the ADL S and P GuC FWs is the HWConfig support. ADL-N does not support HWConfig, so we should use the same binary as ADL-S, otherwise the GuC might attempt to fetch a config table that does not exist. ADL-N is internally identified as an ADL-P, so we need to special-case it in the FW selection code. Fixes: 7e28d0b2 ("drm/i915/adl-n: Enable ADL-N platform") Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220621233005.3952293-1-daniele.ceraolospurio@intel.com
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This test will validate we can achieve actual frequency of RP0. Pcode grants frequencies based on what GuC is requesting. However, thermal throttling can limit what is being granted. Add a test to request for max, but don't fail the test if RP0 is not granted due to throttle reasons. Also optimize the selftest by using a common run_test function to avoid code duplication. Rename the "clamp" tests to vary_max_freq and vary_min_freq. v2: Fix compile warning v3: Review comments (Ashutosh). Added a FIXME for the media RP0 case. v4: Checkpatch (strict) fixes, remove FIXME and other comments (Ashutosh) Fixes commit 8ee2c227 ("drm/i915/guc/slpc: Add SLPC selftest") Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
Vinay Belgaumkar <vinay.belgaumkar@intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220627230346.27720-1-vinay.belgaumkar@intel.com
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- Jul 22, 2022
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2022-07-21' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes pull: * amdgpu: Fix for drm buddy memory corruption * nouveau: PM fixes; DP fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/Ytj65+PdAJs4jIEO@linux-uq9g
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git://linuxtv.org/pinchartl/mediaDave Airlie authored
Miscellaneous R-Car DU fixes and enhancements Signed-off-by:
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- Jul 15, 2022
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User reported gpu page fault when running graphics applications and in some cases garbaged graphics are observed as soon as X starts. This patch fixes all the issues. Fixed the typecast issue for fpfn and lpfn variables, thus preventing the overflow problem which resolves the memory corruption. Signed-off-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reported-by:
Mike Lothian <mike@fireburn.co.uk> Tested-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2022-07-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes: - dma-buf: revert change to fence handling - mgag200: fix PCI register initialization Signed-off-by:
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Dave Airlie authored
Merge tag 'amd-drm-next-5.20-2022-07-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.20-2022-07-14: amdgpu: - DCN3.2 updates - DC SubVP support - DP MST fixes - Audio fixes - DC code cleanup - SMU13 updates - Adjust GART size on newer APUs for S/G display - Soft reset for GFX 11 - Soft reset for SDMA 6 - Add gfxoff status query for vangogh - Improve BO domain pinning - Fix timestamps for cursor only commits - MES fixes - DCN 3.1.4 support - Misc fixes - Misc code cleanup amdkfd: - Simplify GPUVM validation - Unified memory for CWSR save/restore area - fix possible list corruption on queue failure radeon: - Fix bogus power of two warning UAPI: - Unified memory for CWSR save/restore area for KFD Proposed userspace: https://lists.freedesktop.org/archives/amd-gfx/2022-June/080952.html Signed-off-by:
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- Jul 14, 2022
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Lyude Paul authoredWhile trying to fix another issue, it occurred to me that I don't actually think there is any situation where we want pm_runtime_put() in nouveau to be synchronous. In fact, this kind of just seems like it would cause issues where we may unexpectedly block a thread we don't expect to be blocked. So, let's only use pm_runtime_put_autosuspend(). Changes since v1: * Use pm_runtime_put_autosuspend(), not pm_runtime_put() Signed-off-by:
Lyude Paul <lyude@redhat.com>
Reviewed-by: David Airlie <airlied@linux.ie> Fixes: 3a6536c5 ("drm/nouveau: Intercept ACPI_VIDEO_NOTIFY_PROBE") Cc: Hans de Goede <hdegoede@redhat.com> Cc: <stable@vger.kernel.org> # v4.10+ Link: https://patchwork.freedesktop.org/patch/msgid/20220714174234.949259-3-lyude@redhat.com
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Lyude Paul authored
Since this isn't actually a failure. Signed-off-by:
Lyude Paul <lyude@redhat.com>
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Lyude Paul authored
It looks like that when we moved nouveau over to using drm_dp_aux_init() and registering it's aux bus during late connector registration, we totally forgot to fix the failure codepath in nouveau_connector_create() - as it still seems to assume that drm_dp_aux_init() can fail (it can't). So, let's fix that and also add a missing check to ensure that we've properly allocated nv_connector->aux.name while we're at it. Signed-off-by:
Lyude Paul <lyude@redhat.com>
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Thomas Zimmermann authoredRemove the read operation from mgag200_init_pci_options(). It was incorrectly added while refactoring the code. Reading the PCI option register clears the register's new value and subsequently leads to re-writing the old value. Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
Jocelyn Falempe <jfalempe@redhat.com> Fixes: ce19021f ("drm/mgag200: Move PCI-option setup into model-specific code") Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Dave Airlie <airlied@redhat.com> Cc: dri-devel@lists.freedesktop.org Link: https://patchwork.freedesktop.org/patch/msgid/20220708072114.13960-1-tzimmermann@suse.de
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Christian König authored
This reverts commit 8f619737. It turned out that this is not correct. Especially the sync_file info IOCTL needs to see even signaled fences to correctly report back their status to userspace. Instead add the filter in the merge function again where it makes sense. Signed-off-by:
Karolina Drobnik <karolina.drobnik@intel.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220712102849.1562-1-christian.koenig@amd.com
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Thomas Zimmermann authored
Backmerging from drm/drm-next for the final fixes that will go into v5.20. Signed-off-by: -
Alex Deucher authored
Several headers were included twice. Fix that. Reported-by:
kernel test robot <yujie.liu@intel.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
André Almeida <andrealmeid@igalia.com> Signed-off-by:
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Roman Li authored
Add support for DCN 3.1.4 in Display Manager Signed-off-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Roman Li authored
Initialize DMUB for DCN 3.1.4. Use same funcs as DCN31. Signed-off-by:
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Roman Li authored
Add support for DCN 3.1.4 in Display Core Signed-off-by:
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Roman Li authored
DCN 3.1.4 version and family ids Signed-off-by:
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Roman Li authored
Display mode library for DCN 3.1.4 v2: squash in checkpatch fix (Alex) Signed-off-by:
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Roman Li authored
Display Core support for DCN 3.1.4 v2:(squash)fix non-x86 in dc/dcn314/Makefile Properly handle PPC as well. (Alex) v3: minor cleanup (Alex) v4: fix comment (Alex) Signed-off-by:
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Roman Li authored
Clock and SMU interfaces for DCN 3.1.4 Signed-off-by:
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Roman Li authored
IRQ services to support DCN 3.1.4 interrupts. v2: make to_dal_irq_source_dcn314 static (Alex) Signed-off-by:
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Roman Li authored
Register headers for the following IPs: - DCN 3.1.4 - DPCS 3.1.4 v2:(squash) clean up (Alex) Signed-off-by:
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Michel Dänzer authored
Requires enabling the vblank machinery for them. Bug: drm/amd#2030 Acked-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Leo Li authoredWhen pinning a buffer, we should check to see if there are any additional restrictions imposed by bo->preferred_domains. This will prevent the BO from being moved to an invalid domain when pinning. For example, this can happen if the user requests to create a BO in GTT domain for display scanout. amdgpu_dm will allow pinning to either VRAM or GTT domains, since DCN can scanout from either or. However, in amdgpu_bo_pin_restricted(), pinning to VRAM is preferred if there is adequate carveout. This can lead to pinning to VRAM despite the user requesting GTT placement for the BO. v2: Allow the kernel to override the domain, which can happen when exporting a BO to a V4L camera (for example). Signed-off-by:
Leo Li <sunpeng.li@amd.com>
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- Jul 13, 2022
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Alex Deucher authored
The indentation is screwed up. I'm not sure quite how the logic should flow. Someone more familiar with this code should verify this. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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André Almeida authoredImplement function to get current GFXOFF status for vangogh. Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Melissa Wen authoredCheck the value of per_pixel_alpha to decide whether the Coverage pixel blend mode is applicable or not. Fixes: 76818cdd ("drm/amd/display: add Coverage blend mode for overlay plane") Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Yefim Barashkin authored
divide error: 0000 [#1] SMP PTI CPU: 3 PID: 78925 Comm: tee Not tainted 5.15.50-1-lts #1 Hardware name: MSI MS-7A59/Z270 SLI PLUS (MS-7A59), BIOS 1.90 01/30/2018 RIP: 0010:smu_v11_0_set_fan_speed_rpm+0x11/0x110 [amdgpu] Speed is user-configurable through a file. I accidentally set it to zero, and the driver crashed. Reviewed-by:
Yefim Barashkin <mr.b34r@kolabnow.com> Signed-off-by:
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Mario Kleiner authored
Various DCE versions had trouble with 36 bpp lb depth, requiring fixes, last time in commit 353ca0fa ("drm/amd/display: Fix 10bit 4K display on CIK GPUs") for DCE-8. So far >= DCE-11.2 was considered ok, but now I found out that on DCE-11.2 it causes dithering when there shouldn't be any, so identity pixel passthrough with identity gamma LUTs doesn't work when it should. This breaks various important neuroscience applications, as reported to me by scientific users of Polaris cards under Ubuntu 22.04 with Linux 5.15, and confirmed by testing it myself on DCE-11.2. Lets only use depth 36 for DCN engines, where my testing showed that it is both necessary for high color precision output, e.g., RGBA16 fb's, and not harmful, as far as more than one year in real-world use showed. DCE engines seem to work fine for high precision output at 30 bpp, so this ("famous last words") depth 30 should hopefully fix all known problems without introducing new ones. Successfully retested on DCE-11.2 Polaris and DCN-1.0 Raven Ridge on top of Linux 5.19.0-rc2 + drm-next. Fixes: 353ca0fa ("drm/amd/display: Fix 10bit 4K display on CIK GPUs") Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Tested-by:
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Alex Deucher authored
Not used outside of dc_dmub_srv.c. Reported-by:
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Alex Deucher authored
Drop execute. Bug: drm/amd#2085 Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Kent Russell authored
The initialism of RunList Controller is RLC, not RCL Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Aric Cyr authored
This version brings along following fixes: - Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others - Add register offsets of NBI and DCN. - Improvement of ALPM - Removing assert statement for Linux DM - Re-implementing ARGB16161616 pixel format Acked-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Samson Tam authored
[Why] With single display odm 2:1 policy, when moving windowed MPO across the display, we experience a momentary lag when we move between the centre of the display and the right half of the display. This is caused by the MPO pipe being reallocated when it crosses this boundary [How] Handle two cases: 1. if the head pipe has a MPO pipe already allocated in the old context, then use that pipe if it is available in the current context 2. if the head pipe is on the left side, check the right side to see if it has a MPO pipe already allocated. If so, don't use that pipe if it is selected as the idle pipe in the current context Add new function pointer called .acquire_idle_pipe_for_head_pipe that will pass in the head pipe and handle case 1 Add find_idle_secondary_pipe_check_mpo() to handle case 2 if we don't hit case 1. In dc_add_plane_to_context(), start with head pipe and check case 1 and 2 in call acquire_free_pipe_for_head(). If we are on the right side of the display, check case 1 again by passing in right side pipe as the new head in call acquire_free_pipe_for_head(). Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] Add a field to store the NBIO IP offset for use with runtime offset calculation Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Harry Wentland authored[Why&How] Add a field to store the DCN IP offset for use with runtime offset calculation This offset is indexed using reg*_BASE_IDX for the corresponding group of registers. For example, address of DIG_BE_CNTL instance 0 is calculated like: dcn_reg_offsets[regDIG0_DIG_BE_CNTL_BASE_IDX] + regDIG0_DIG_BE_CNTL. {dcn,nbio}_reg_offsets are used only for the ASICs for which runtime initializaion of offsets are enabled through the modified SR* macros that contain an additional REG_STRUCT element in the macro definition. DCN3.5+ will fail dc_create() if {dcn,nbio}_reg_offsets are null. They are applicable starting with DCN32/321 and are not used for ASICs upstreamed before them. ASICs before DCN32/321 will not contain any computation that involves {dcn,nbio}_reg_offsets. For them, the address/offset computation is done during compile time. This is evident from the BASE_INNER definition for compile time vs run time initialization: Compile time init: #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg Run time init: #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] BASE_INNER macro is local to each dcnxx_resource.c and hence different ASICs can have either runtime or compile time initialization of offsets. The computation of offset is done for registers all at once during driver load and hence it does not introduce any performance overhead during normal operation. Reviewed-by:
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