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  • Simona Vetter Simona Vetter sima
1 author
  1. Feb 15, 2019
  3. Feb 14, 2019
    • Ramalingam C's avatar
      kms_content_protection: Macros replace the constants · 395eaffd
      Ramalingam C authored 
      
For better readability, numeric values are replaced with macros.

Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      395eaffd
    • Ramalingam C's avatar
      kms_content_protection: Confirm that LIC is passed · fd5b0534
      Ramalingam C authored 
      
Once the HDCP is enabled, kernel will run the link integrity check(LIC)
atleast once in 2Secs based on the HDCP versions.

So to confirm the link integrity check is passed, we oberve that HDCP
state remains ENABLED for next 4Secs.

v2:
  Rebased.

Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      fd5b0534
    • Ramalingam C's avatar
      kms_content_protection: Test CP along with modeset · d4c40ff0
      Ramalingam C authored 
      
As we have two different patch for commitng the HDCP request
	1. DDI_enable (during the modeset)
	2. update_pipe (during fastset execution)

Currently our kms_content_protection covers only fastset path.
So this test adds the coverage for the HDCP during the modeset by
performing DPMS off-on and check for HDCP status.

But with respect to HDCP we allow few retries from userspace before
reporting the failure. So only first attempt at kernel will be on
modeset path, next retries will become fastset commiting of HDCP.

v2:
  dpms test is added within existing implementation with a flag [Daniel]
v3:
  ret declared.

Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d4c40ff0
    • Ramalingam C's avatar
      kms_content_protection: modularizing the CP test steps · bc20c44c
      Ramalingam C authored 
      
Modularizing the CP test steps for the convenience of reusing it for
other subtests.

Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      bc20c44c
    • José Roberto de Souza's avatar
      test: Add PSR2 selective update tests · eea5cf40
      José Roberto de Souza authored 
      
This tests checks if hardware is able to do selective update when
screen changes.
PSR2 don't trigger interruptions and the 'PSR2 SU status' register
is not kept loaded all the times, so it is necessary keep polling
PSR status debugfs until those values are loaded.

Also from DEEP_SLEEP state HW will not do a seletive update, as
most of the memory/context is lost in deep sleep state hardware will
need to exit PSR mode then wait a configured number of frames to
activate PSR again to then start doing seletive updates, that is why
just one screen change is not enough to pass this tests.

When a selective update happens and the values are loaded and read
from debugfs it is compared with the expected value of seletive
update blocks, if matches the polling is stopped and the test passed
otherwise it will wait until it reachs a maximum number o screen
changes to fail the test.

v2: Using new SU blocks debugfs output

v3:
- removed the timerfd to fail the test, now failing based in a
maximum number of screen changes
- removing thread to read debugfs, read from main thread is enough
- improved commit message

v4:
- getting cairo context for frontbuffer test in prepare()
- droppoing poll(), using blocking timerfd instead

v5:
- Doing a modeset before trying to enable PSR2

v6:
- doing atomic commits to fix(legacy commit is taking more time in
recent kernels causing us to miss the SU when reading debugfs) and
speedup test
- fixed code to skip test when PSR2 is not possile

Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Tested-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
      eea5cf40
  5. Feb 13, 2019
  7. Feb 12, 2019
  9. Feb 11, 2019
  11. Feb 08, 2019
  13. Feb 07, 2019