i965: Prevent coordinate overflow in intel_emit_linear_blit
Fixes regression from commit 8c17d538 Author: Kenneth Graunke <kenneth@whitecape.org> Date: Wed Apr 15 03:04:33 2015 -0700 i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions. which adjusted the coordinates to be relative to the nearest cacheline. However, this then offsets the coordinates by up to 63 and this may then cause them to overflow the BLT limits. For the well aligned large transfer case, we can use 32bpp pixels and so reduce the coordinates by 4 (versus the current 8bpp pixels). We also have to be more careful doing the last line just in case it may exceed the coordinate limit. Reported-and-tested-by:<kaillasse91@hotmail.fr> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90734 Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Kenneth Graunke <kenneth@whitecape.org> Cc: Ian Romanick <ian.d.romanick@intel.com> Cc: Anuj Phogat <anuj.phogat@gmail.com> Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Anuj Phogat <anuj.phogat@gmail.com>