i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. intel_emit_linear_blit needs to handle blits that are not cacheline aligned, as we use it for arbitrary glBufferSubData calls and subrange mappings. Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst pixel X offset field to represent the unaligned portion, and subtract that from the address so it's cacheline aligned. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by:Kenneth Graunke <kenneth@whitecape.org> Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Reviewed-by:
Anuj Phogat <anuj.phogat@gmail.com> Cc: mesa-stable@lists.freedesktop.org