- Aug 19, 2021
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Dylan Baker authored
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Dylan Baker authored
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- Aug 18, 2021
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Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Acked-by: Daniel Stone <daniels@collabora.com> Part-of: <!12391> (cherry picked from commit f378799d) Conflicts: .gitlab-ci/windows/quick_gl.txt
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Dylan Baker authored
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- Aug 17, 2021
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Fixes: a4dafe1f "intel/isl: Make the offset helpers four dimensional" Acked-by: Ivan Briano <ivan.briano@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!11765> (cherry picked from commit eb7c28bf)
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The only user of this case is iris which initializes offset_B to 0 so there's no real bug here. However, it is unexpected from an API PoV. Fixes: 9946120d "intel/isl: Add more cases to isl_surf_get_uncompressed_surf" Acked-by: Ivan Briano <ivan.briano@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!11765> (cherry picked from commit 37024061)
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Currently stride, offset, modifier is obtained by invoking lima_resource_get_handle() with WINSYS_HANDLE_TYPE_KMS. Before commit 47f000c1 this path was working. Obtained handle was simply ignored by DRI frontend and only requested data used. After commit 47f000c1 such requests started to fail when DRI is initialized using KMSRO and resource has no scanout data. When lima_resource_get_param() is implemented, it will be used in a first place to obtain resource data. Fixes: 47f000c1 ("lima: fail in get_handle(TYPE_KMS) without a scanout resource") Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com> Reviewed-by: Simon Ser <contact@emersion.fr> Reviewed-by: Erico Nunes <nunes.erico@gmail.com> Part-of: <mesa/mesa!12362> (cherry picked from commit 5ec6b6e9)
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When operators other than eq and ne are involved we can't really move operands around and negate them because such transformation may change the value of the whole expression. Some examples: For unsigned var: 0 >= 1u + var would eventually become 0xffffffff >= var, which would always evaluate to true, when original expression was true only for var == 0xffffffff. For signed var: 0 >= 1 + var would become -1 >= var, which would evaluate to false for var == 2147483647, when original expression evaluated to true (because signed overflow is defined to wrap around in glsl, 1 + 2147483647 == -2147483648, so 0 >= -2147483648). Closes: mesa/mesa#5226 Fixes: 34ec1a24 ("glsl: Optimize (x + y cmp 0) into (x cmp -y).") Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <mesa/mesa!12359> (cherry picked from commit 89bc8ff4)
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Dylan Baker authored
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- Aug 16, 2021
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At the beginning of a render pass, the hardware will fill the tilebuffer with an arbitrary 128-bit word. To implement colour clears, the driver must pack the API-specific clear colour according to the 128-bit layout of the tilebuffer. This layout depends only on the render target format. The existing code to handle this was based on loose guesswork. It works for the format / clear colour combinations tested in dEQP-GLES3, but it is severely deficient in the general case. It works by matching on the PIPE format of the render target (not the layout of the tilebuffer). For special cased PIPE formats, it open codes a buggy pack routine. Otherwise, it defaults to util_pack_color in the hope that will work. Since util_pack_color doesn't know anything about Mali tilebuffer layouts, that means it's defaulting to wrong behaviour. Now that we understand internal tilebuffer layouts, let's rewrite the packing code. Instead of matching PIPE formats, map the PIPE format to the internal tilebuffer layout using the common table, ensuring the mapping remains in sync with the render target descriptor. Then for blendable tilebuffer formats, pack using a common float -> fixed point path supporting optional sRGB translation. Raw formats use util_pack_color as before. For formats with less than 8 bits per channel, the new code uses the fractional bits of the fixed-point representation. This is required for correct dithering if the clear colour is not exactly representable in the final low precision format. In summary, at least the following bugs in the old code are fixed: * Swapped R/B channels with sRGB * Swapped R/B channels with some missing formats * Incorrect dithering with RGB565, RGB5_A1 Fixes the following test cases: dEQP-EGL.functional.wide_color.window_8888_colorspace_srgb dEQP-EGL.functional.wide_color.pbuffer_8888_colorspace_srgb dEQP-EGL.functional.wide_color.window_888_colorspace_srgb dEQP-EGL.functional.wide_color.pbuffer_888_colorspace_srgb Later in the series, unit tests are added for the new implementation. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Cc: mesa-stable Part-of: <mesa/mesa!12365> (cherry picked from commit b9c095cc) Conflicts: src/panfrost/lib/pan_util.h
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Fixes timeouts in SuperTuxKart with the advanced rendering pipeline. Fixes: d0344619 ("panfrost: Set allow_forward_pixel_to_be_killed for blit") Part-of: <mesa/mesa!12267> (cherry picked from commit 0624346a)
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Transfer ownership of the render node fd to the panfrost_device (minor change to panvk), and then close the file descriptor for the render node bound to the panfrost_device when destroying the panfrost_device. Of all the users of panfrost_open_device, panvk is the only one that correctly closed the fd before. Accordingly, this fixes an fd leak in the Gallium driver (and performance counter utilities). This fix still applies to the Gallium driver when renderonly is in use-- although renderonly closes its own fd, the fd is _duplicated_ in panfrost_drm_winsys.c, so renderonly and panfrost must _both_ close their respective fd to fix the leak. This fixes a crash when running dEQP-EGL for more than two hours. dEQP-EGL creates a new screen for every test case and then immediately destroys it. If destroying a screen leaks the fd, this causes the number of open file descriptors to increase monotonically until the process ends. This will eventually hit the system limit for number of open files and abort the process. This bug was identified while attempting to run the OpenGL ES conformance tests via cts-runner, and then confirmed with `lsof`. With the fix, the number of file descriptors reported by `lsof | wc -l` is now constant while running dEQP-EGL as expected. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Cc: mesa-stable Part-of: <mesa/mesa!12346> (cherry picked from commit 76377de9)
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Fixes warning during the build and unnecessary rule execution: *** ninja: Missing `restat`? An output file is older than the most recent input: *** Fixes: 8621bd8d ("android: Add scripts to build using meson") Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com> Tested-by: Mauro Rossi <issor.oruam@gmail.com> Part-of: <mesa/mesa!12304> (cherry picked from commit 21de7855)
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mesa3d require up-to-date version of libdrm. Hardcoding it to 2.4.105 is wrong. Fixes: 8621bd8d ("android: Add scripts to build using meson") Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com> Tested-by: Mauro Rossi <issor.oruam@gmail.com> Part-of: <mesa/mesa!12304> (cherry picked from commit a70ff21e)
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Fixes: cf9ff082 ("isl: Bring back isl_format_layout::bpb") Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Part-of: <mesa/mesa!3674> (cherry picked from commit 773a70f9)
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This reverts commit ad363913. This code was added to be able to compare the output file while porting the script from python2 to python3, but this has long been finished and the extra complexity is not needed anymore. Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Part-of: <mesa/mesa!3674> (cherry picked from commit 93cb3aca)
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mmap requires its offset is page aligned, but the current code only guarantees 4k alignment, causing drm-shim to break badly on kernels with >4k page sizes. This fixes drm-shim on my Apple M1, running bare metal Linux with 16k pages. It probably also fixes exotic PowerPC systems with 64k pages. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Zoltan Boszormenyi <zboszor@gmail.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Emma Anholt <emma@anholt.net> Cc: mesa-stable Part-of: <mesa/mesa!12347> (cherry picked from commit 38f39cc1)
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Dylan Baker authored
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- Aug 13, 2021
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Cc: 21.2 mesa-stable Reviewed-by: Joshua Ashton <joshua@froggi.es> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Closes #5092 Part-of: <mesa/mesa!12178> (cherry picked from commit e4c0a34b)
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When creating an image out of a swapchain on Android, the android layer call will detect a VkBindImageMemorySwapchainInfoKHR in the pNext chain of the vkBindImageMemory2() call and add a VkNativeBufferANDROID in the chain. This is what we should use as backing memory for that image. v2: Fix a couple of obvious mistakes (Tapani) v3: Silence build warning (Lionel) Fix invalid object argument to vk_error() (Lionel) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: bc3c71b8 ("anv: don't try to access Android swapchains") Cc: mesa-stable Closes: mesa/mesa#5180 Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <mesa/mesa!12244> (cherry picked from commit 19b7bbba)
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Fix defect reported by Coverity Scan. Uninitialized scalar variable (UNINIT) uninit_use: Using uninitialized value dst.x. Fixes: a1a2a8df ("nir: add AMD_gcn_shader extended instructions") Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!12290> (cherry picked from commit 8d679f4f)
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Fixes: d30ce03b ("meson: add build-summary") Signed-off-by: Vinson Lee <vlee@freedesktop.org> Part-of: <!12296> (cherry picked from commit c0fc745b)
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Since 2b5178ee util: Switch the non-block formats to unpacking rgba rows instead of rects, compressed formats define unpack_rgba_8unorm_rect instead of unpack_rgba_8unorm. Fixes the u_format_translate check to take this into account. Closes: mesa/mesa#5201 Fixes: 2b5178ee ("util: Switch the non-block formats to unpacking rgba rows instead of rects") Signed-off-by: Axel Davy <davyaxel0@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!12315> (cherry picked from commit 6a0e7035)
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Dylan Baker authored
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- Aug 12, 2021
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Before a73cb106, cso contexts were never reused, but now that they are we need to be extra careful that the state in the cso context and in the pipe context matches even after an unbind, since when the cso context is reused the state might otherwise get out of sync (as there is no concept of "initial state", basically cso always relied on the default values being the same both in cso and the drivers). This fixes some errors we've seen internally with lavapipe. Fixes: a73cb106 ("aux/cso: split cso_destroy_context into unbind and a destroy functions") Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!12261> (cherry picked from commit 513fb543)
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On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented using a separte cmpn and sel instruction. This lowering occurs in fs_vistor::lower_minmax which is called very, very late... a long, long time after the first calls to opt_cmod_propagation. As a result, conditional modifiers can be incorrectly propagated across sel.cond on those platforms. No tests were affected by this change, and I find that quite shocking. After just changing flags_written(), all of the atan tests started failing on ILK. That required the change in cmod_propagatin (and the addition of the prop_across_into_sel_gfx5 unit test). Shader-db results for ILK and GM45 are below. I looked at a couple before and after shaders... and every case that I looked at had experienced incorrect cmod propagation. This affected a LOT of apps! Euro Truck Simulator 2, The Talos Principle, Serious Sam 3, Sanctum 2, Gang Beasts, and on and on... :( I discovered this bug while working on a couple new optimization passes. One of the passes attempts to remove condition modifiers that are never used. The pass made no progress except on ILK and GM45. After investigating a couple of the affected shaders, I noticed that the code in those shaders looked wrong... investigation led to this cause. v2: Trivial changes in the unit tests. v3: Fix type in comment in unit tests. Noticed by Jason and Priit. v4: Tweak handling of BRW_OPCODE_SEL special case. Suggested by Jason. Fixes: df1aec76 ("i965/fs: Define methods to calculate the flag subset read or written by an fs_inst.") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Dave Airlie <airlied@redhat.com> Iron Lake total instructions in shared programs: 8180493 -> 8181781 (0.02%) instructions in affected programs: 541796 -> 543084 (0.24%) helped: 28 HURT: 1158 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.35% max: 0.86% x̄: 0.53% x̃: 0.50% HURT stats (abs) min: 1 max: 3 x̄: 1.14 x̃: 1 HURT stats (rel) min: 0.12% max: 4.00% x̄: 0.37% x̃: 0.23% 95% mean confidence interval for instructions value: 1.06 1.11 95% mean confidence interval for instructions %-change: 0.31% 0.38% Instructions are HURT. total cycles in shared programs: 239420470 -> 239421690 (<.01%) cycles in affected programs: 2925992 -> 2927212 (0.04%) helped: 49 HURT: 157 helped stats (abs) min: 2 max: 284 x̄: 62.69 x̃: 70 helped stats (rel) min: 0.04% max: 6.20% x̄: 1.68% x̃: 1.96% HURT stats (abs) min: 2 max: 48 x̄: 27.34 x̃: 24 HURT stats (rel) min: 0.02% max: 2.91% x̄: 0.31% x̃: 0.20% 95% mean confidence interval for cycles value: -0.80 12.64 95% mean confidence interval for cycles %-change: -0.31% <.01% Inconclusive result (value mean confidence interval includes 0). GM45 total instructions in shared programs: 4985517 -> 4986207 (0.01%) instructions in affected programs: 306935 -> 307625 (0.22%) helped: 14 HURT: 625 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.35% max: 0.82% x̄: 0.52% x̃: 0.49% HURT stats (abs) min: 1 max: 3 x̄: 1.13 x̃: 1 HURT stats (rel) min: 0.12% max: 3.90% x̄: 0.34% x̃: 0.22% 95% mean confidence interval for instructions value: 1.04 1.12 95% mean confidence interval for instructions %-change: 0.29% 0.36% Instructions are HURT. total cycles in shared programs: 153827268 -> 153828052 (<.01%) cycles in affected programs: 1669290 -> 1670074 (0.05%) helped: 24 HURT: 84 helped stats (abs) min: 2 max: 232 x̄: 64.33 x̃: 67 helped stats (rel) min: 0.04% max: 4.62% x̄: 1.60% x̃: 1.94% HURT stats (abs) min: 2 max: 48 x̄: 27.71 x̃: 24 HURT stats (rel) min: 0.02% max: 2.66% x̄: 0.34% x̃: 0.14% 95% mean confidence interval for cycles value: -1.94 16.46 95% mean confidence interval for cycles %-change: -0.29% 0.11% Inconclusive result (value mean confidence interval includes 0). Part-of: <mesa/mesa!12191> (cherry picked from commit 38807cee)
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Aligning the pitch to 4 bytes allows the BLT engine to be used for transfers to/from these surfaces. Fixes: f3630548 ("crocus: initial gallium driver for Intel gfx 4-7") Part-of: <mesa/mesa!12329> (cherry picked from commit 593ad929)
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I lost these in my conversion from i965 but they are necessary. This should fix corruption in qt fonts at seen in the minecraft launcher. Fixes: f3630548 ("crocus: initial gallium driver for Intel gfx 4-7") Part-of: <mesa/mesa!12329> (cherry picked from commit 58e95f99)
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Dylan Baker authored
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Per mesa/mesa#5178 (comment 1019666) , the assumption fundamental to this optimization is false. Section 2.4.1 (Float to Integer) of Ivy Bridge PRMs describes the situation. The wording of the section is somewhat confusing (because it doesn't clearly delineate between signed and unsigned integers), but the last two rows of the table make it clear that F->UD conversion clamps negative float values to 0. All other hardware mentioned in that thread seems to behave the same way. The real problem is that, with hardware that behaves in this ways, converting f2u(2147483648.0) to f2i(2147483648.0) changes the bit pattern that would be produced from 0x80000000 to 0x7fffffff. This reverts commit ad059202. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!12297> (cherry picked from commit 84d2e537)
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This is confusing opt_cse. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 8dfb240b ("nir: Add raytracing shader call lowering pass.") Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <mesa/mesa!11953> (cherry picked from commit 01b0935d)
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Fixes: a62098ff ("nir: Add a helper for general instruction-modifying passes.") Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!12324> (cherry picked from commit e1b325f5)
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This makes pow(NaN, x) return NaN rather than 1.0. Fixes: 49939770 ("pan/bi: Don't lower fpow") Closes: mesa/mesa#5189 Part-of: <mesa/mesa!12269> (cherry picked from commit ee2bb57f)
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With our ff-only merge setup, the commit date ends up being when the commit actually landed (as opposed to when it was first written). Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Cc: mesa-stable Part-of: <!12289> (cherry picked from commit 4128acde)
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Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Cc: mesa-stable Part-of: <mesa/mesa!12289> (cherry picked from commit 7ec42b5e)
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Let's just make it not-optional instead. Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Cc: mesa-stable Part-of: <mesa/mesa!12289> (cherry picked from commit db14f2a9)
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Fixes: fb29cef8 ("nir: add many passes that lower and optimize 16-bit input/outputs and samplers") Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!11732> (cherry picked from commit 9b57a818)
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Otherwise drivers that don't use 16-bit slots for varyings will get confused and have their driver_locations scribbled over. This has caused multiple problems for both Panfrost and Asahi this week. Given the only other user of the pass for varyings is radeonsi, which needs both together, I think this is the least controversial fix. Fixes: fb29cef8 ("nir: add many passes that lower and optimize 16-bit input/outputs and samplers") Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!11732> (cherry picked from commit 03c18f7e)
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Dylan Baker authored
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- Aug 11, 2021
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Tapani Pälli authored
This is similar to i965 commit ba11f673, we set depth and d+s formats unsupported for now. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!12330>
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