- Mar 05, 2020
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Dylan Baker authored
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Dylan Baker authored
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- Mar 04, 2020
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This reverts commit 35fc7bdf. Unfortunately mentioned commit introduced a memory leak because `driwindowsMapConfigs` and `createDriMode` functions allocate small memory portions for each element: 21,576 (232 direct, 21,344 indirect) bytes in 1 blocks are definitely lost in loss record 1,411 of 1,414 at 0x483A7F3: malloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so) by 0x5D4AA09: createDriMode (dri_common.c:291) by 0x5D4ABF5: driConvertConfigs (dri_common.c:310) by 0x5D58414: dri3_create_screen (dri3_glx.c:945) by 0x5D39829: AllocAndFetchScreenConfigs (glxext.c:815) by 0x5D39C57: __glXInitialize (glxext.c:941) by 0x5D3290A: GetGLXPrivScreenConfig (glxcmds.c:174) by 0x5D34F38: glXQueryExtensionsString (glxcmds.c:1307) by 0x4F83038: glXQueryExtensionsString (in /usr/local/lib/libGL.so.1.7.0) by 0x4F2EA6B: ??? (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.6.0) by 0x4F2A0D7: waffle_display_connect (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.6.0) by 0x498F42A: wfl_checked_display_connect (piglit-util-waffle.h:74) There is one more thing which disallow us to easily fix it are different element sizes for instance: `glx_config_create_list` allocates memory just for `glx_config`, `driwindowsMapConfigs` for `driwindows_config` and `createDriMode` for `__GLXDRIconfigPrivate`. Yes it is possible but size of such fix will be more big and complex than original one. So it make sense only if the malloc overhead really is a big problem there. Acked-by: Eric Engestrom <eric@engestrom.ch> Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3406> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3406> (cherry picked from commit 311c82e1)
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Fixes a GPU hang in Car Chase. Cc: mesa-stable@lists.freedesktop.org v2: Add comment explaining why (Jason). Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <mesa/mesa!4035> Part-of: <mesa/mesa!4035> (cherry picked from commit 5f139962)
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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-By: Timur Kristóf <timur.kristof@gmail.com> Fixes: e0bcefc3 ('aco/wave32: Use lane mask regclass for exec/vcc.') Part-of: <mesa/mesa!3902> (cherry picked from commit 215df21d)
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And properly handle unordered events so that they always wait for 0. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler') Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Tested-by: Marge Bot <mesa/mesa!3774> Part-of: <mesa/mesa!3774> (cherry picked from commit 9fea90ad)
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Found by inspection, I'm not aware of any bugs caused by this typo. According to Lionel, it seems we only use this to generate masks of available EUs for perfromance queries, and it's only used when we can't query the fused parts of the GPU through DRM_IOCTL_I915_QUERY. So this patch should help for the corner case where the Kernel is too old to support the query ioctl. v2: improve commit message, cc stable (Lionel). Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <mesa/mesa!4006> (cherry picked from commit aa78801f)
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This is the same idea as "intel: fix the gen 11 compute shader scratch IDs". The number of EUs on TGL is not the same as ICL, but the MEDIA_VFE_STATE restrictions stay the same, so adapt the code to it. Also, consider the base configuration instead of what we read from the Kernel. According to Mark, this fixes the following piglit tests on TGL: piglit.spec.arb_compute_shader.execution.shared-atomicmax-uint.tglm64 piglit.spec.arb_compute_shader.execution.shared-atomicmax-int.tglm64 piglit.spec.intel_shader_atomic_float_minmax.execution.shared-atomicmax-float.tglm64 v2: s/ICL+/Gen11+/ (Jason). Cc: mesa-stable@lists.freedesktop.org Tested-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <mesa/mesa!4006> (cherry picked from commit 9e5ce30d)
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Scratch space allocation is based on the number of threads in the base configuration, and we only have one base configuration for ICL, with 8 subslices. This fixes an issue with Aztec on Vulkan in a machine with a configuration that's not the base. The issue looks like a regression from b9e93db2, but it seems things are broken since forever, just not easily reproducible. v2: Reimplement it using the subslices variable. Don't touch TGL. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <mesa/mesa!4006> (cherry picked from commit 1efe139c)
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Dylan Baker authored
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- Mar 02, 2020
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Earlier commit did not take in to account that lists required for rendering and texturing are parsed separately. This commit simply removes formats added to the other list. Fixes: de4eb9a3 ("mesa/st: toggle EXT_texture_norm16 based on format support") Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Marge Bot <mesa/mesa!3961> Part-of: <mesa/mesa!3961> (cherry picked from commit fbd61b3f)
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Our current GPGPU_WALKER code only supports up to 64 threads. On HSW we could use up to 70 and TGL up to 112, but only if the walker is adjusted so the width does not exceed 64. Work to support this is in progress. Previous to this change, we might try to downgrade to SIMD8 if the SIMD16 shader spilled. Since HSW and TGL have the max number of threads above 64, we would then try to emit an invalid GPGPU walker command. Fixes: 93204506 ("i965/cs: Emit compute shader code and upload programs") Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (cherry picked from commit cf12faef)
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Dylan Baker authored
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- Feb 28, 2020
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Marek Olšák authored
This has no effect on Gallium, but it affects tnl. Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de> Tested-by: Marge Bot <mesa/mesa!3990> Part-of: <mesa/mesa!3990> (cherry picked from commit 1a61a5b1) Conflicts Resolved by Dylan Baker Conflicts: src/mesa/main/draw.c
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Register packing macros makes this only set the first bit. Set to whole dword to fix srgb for color attachments >0. Fixes: 59f29fc8 ("turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net> Part-of: <mesa/mesa!3979> (cherry picked from commit 6420406f)
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Emma Anholt authored
The previous instance of this comparision was 1u to avoid the warning, fix this one too. Fixes: dba71de5 ("aco: only create parallelcopy to restore exec at loop exit if needed") Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <mesa/mesa!3607> (cherry picked from commit b9773631)
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The hardware doesn't flush denorms, exactly like fmin/fmax, so we have to do it manually. This doesn't fix anything known. Fixes: d6a07732 ("ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Tested-by: Marge Bot <mesa/mesa!3962> Part-of: <mesa/mesa!3962> (cherry picked from commit 9e5d2a73)
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16-bit med3 is only supported on GFX9+. Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.mid3.f16.*. Fixes: d6a07732 ("ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!3962> (cherry picked from commit 30ac7336)
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Lower 64-bit fmed3 because LLVM doesn't expose an intrinsic. Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.mid3.f64.*. Fixes: d6a07732 ("ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!3962> (cherry picked from commit 50b8c252)
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Mathias Fröhlich authored
Reviewed-by: Marek Olšák <marek.olsak@amd.com> CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de> Tested-by: Marge Bot <mesa/mesa!3958> Part-of: <mesa/mesa!3958> (cherry picked from commit 636656bc)
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I haven't seen this crash but TGSI does it so best align with it to avoid future issues. Fixes: 44a6b0107b3J (gallivm: add nir->llvm translation (v2)) Reviewed-by: Roland Scheidegger <sroland@vmware.com> Tested-by: Marge Bot <mesa/mesa!3956> Part-of: <mesa/mesa!3956> (cherry picked from commit 2b155b10)
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Blender was crashing with a SIGFPE even though the divide by 0 logic was kicking in. I'm not sure why TGSI doesn't get into this state. The problem was is the numerator was INT_MIN we'd replace the div by 0 with a divide by -1, which is an exception for INT_MIN as INT_MIN/-1 == INT_MAX + 1 (too large for 32-bits). Instead for integer divides just replace the mask values with 0x7fffffff. Also fix up the result handling so it aligns with TGSI usage. (gives 0) Fixes: c717ac12 ("gallivm/nir: wrap idiv to avoid divide by 0 (v2)") Reviewed-by: Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!3956> (cherry picked from commit 5370c685)
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This broke TGSI GS shaders with llvmpipe, it wasn't looking at the right immediates and it should be cast to an integer type. Fixes: 163d5fde (gallium/swr: Enable GL_ARB_gpu_shader5: multiple streams) Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com> Acked-by: Jan Zielinski <jan.zielinski@intel.com> Tested-by: Marge Bot <mesa/mesa!3949> Part-of: <mesa/mesa!3949> (cherry picked from commit 954cf8e8)
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Marek Olšák authored
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de> Cc: 20.0 <mesa-stable@lists.freedesktop.org> Tested-by: Marge Bot <mesa/mesa!3947> Part-of: <mesa/mesa!3947> (cherry picked from commit 4449611f)
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Even though the workaround description says: "all the listed commands are non-pipelined and hence flush caused due to pipeline mode change must not cause performance issues..." My understanding is that we still need to have the flushes. Also, the flushes are required not only to stall the pipeline, but also to clear caches, so I don't think they can simply be discarded. Additionally, while doing some testing that increased the number of surface STATE_BASE_ADDRESS emitted, I got a lot more GPU hangs. Adding these flushes fixes those hangs. Fixes: b8fbb39a (iris: Implement Gen12 workaround for non pipelined state) Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <mesa/mesa!3908> Part-of: <mesa/mesa!3908> (cherry picked from commit a70a605a)
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Marek Olšák authored
This fixes the copy_uv shader from st/omx, because it uses image 0 and 2 and image 1 isn't declared. Cc: 20.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Tested-by: Marge Bot <mesa/mesa!3936> Part-of: <mesa/mesa!3936> (cherry picked from commit c798aae7)
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Emma Anholt authored
Fixes: 1c5d84fc ("turnip: hook up cmdbuffer event set/wait") Tested-by: Marge Bot <mesa/mesa!3916> Part-of: <mesa/mesa!3916> (cherry picked from commit bd53f4f5)
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Closes: mesa/mesa#2556 Fixes: 7f467d4f ("mesa: GL_EXT_texture_norm16 extension plumbing") Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Tested-by: Marge Bot <mesa/mesa!3941> Part-of: <mesa/mesa!3941> (cherry picked from commit de4eb9a3)
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Fixes: 7f467d4f ("mesa: GL_EXT_texture_norm16 extension plumbing") Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!3941> (cherry picked from commit 200a83a9)
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Fixes: 7f467d4f ("mesa: GL_EXT_texture_norm16 extension plumbing") Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!3941> (cherry picked from commit dc531869)
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Mathias Fröhlich authored
The __DRI_IMAGE_FORMAT_* part wants to be handled for the *101010 type formats as well. Factor out a common function for that task. That again makes the piglit egl_ext_device_base test work again for hardware drivers. v2: Factor out a common function for that task. v3: dri2_pbuffer_visuals -> dri2_pbuffer_visuals Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Fixes: 9acb94b6 "egl: Enable 10bpc EGLConfigs for platform_{device,surfaceless}" Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de> Part-of: <mesa/mesa!3790> (cherry picked from commit d32c458d)
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Faith Ekstrand authored
Because we set the needs_data_cache bit from the NIR during compilation, any time a shader was pulled out of the pipeline cache, we wouldn't set the bit and the data cache was disabled. Fortunately, on Gen8+, this bit is ignored because we always use the ALL section in the L3$ config instead of separate DC and RO sections. On Gen7, however, this meant that we were basically never running with the data cache enabled and our compute performance was suffering massively because of it. This commit improves Geekbench 5 scores on my Haswell GT3 by roughly 330% (no, that's not a typo). Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <mesa/mesa!3912> Part-of: <mesa/mesa!3912> (cherry picked from commit 5dfd83d7)
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Dylan Baker authored
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- Feb 25, 2020
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When a resource is written by a compute shader and then used by a non-compute stage we sync on last compute job to guarantee that the resource has been completely written when the next stage reads resources. In the other cases how flushes are done guarantee the serialization of the writes and reads. To reproduce the failure the following tests should be executed in batch as last test don't fail when run isolated: KHR-GLES31.core.shader_image_load_store.basic-allFormats-load-fs KHR-GLES31.core.shader_image_load_store.basic-allFormats-loadStoreComputeStage KHR-GLES31.core.shader_image_load_store.basic-allTargets-load-cs KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray v2: Use fence dep instead of bo_wait (Eric Anholt) v3: Rename struct names (Iago Toral) Document why is not needed on graphics->compute case. (Iago Toral) Follow same code pattern of the other update of in_sync_bcl. v4: Fixed comments style. (Iago Toral) Fixes KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> CC: 19.3 20.0 <mesa-stable@lists.freedesktop.org> Tested-by: Marge Bot <mesa/mesa!2700> Part-of: <mesa/mesa!2700> (cherry picked from commit 01496e3d)
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Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de> Cc: <mesa-stable@lists.freedesktop.org> Part-of: <mesa/mesa!3884> (cherry picked from commit 31a80756)
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The fallback to the non-shm put path used the wrong width here as the pixmap is still allocated in a shared segment, so the width needs to reflect that. Fixes: 02c3dad0 ("Call shmget() with permission 0600 instead of 0777") Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> Tested-by: Marge Bot <mesa/mesa!3823> Part-of: <mesa/mesa!3823> (cherry picked from commit 84395190)
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If an attempt to create an shm pixmap in XCreateDrawable fails then it ends up with the shmid == -1. This means the get image path needs to fallback so return false in this case to use the non-shm get image path. Fixes: 02c3dad0 ("Call shmget() with permission 0600 instead of 0777") Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> Part-of: <mesa/mesa!3823> (cherry picked from commit 246e4aea)
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This adds return values to the get image path, so the caller can fallback. Fixes: 02c3dad0 ("Call shmget() with permission 0600 instead of 0777") Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> Part-of: <mesa/mesa!3823> (cherry picked from commit 8d0bab8a)
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When Brian in 02c3dad0 restricted the shm permissions it means we hit the fallback paths in some scenarios we hadn't before. When you use Xephyr to xdmcp from one user to another the new perms stop the X server (running as user a) attaching to the SHM segments from gnome-shell (running as user b). In this case however only the GLX side of the code had insight into this, and the dri could was meant of fall back, and it worked for put image fine but the get image path was broken, since there was no indication in the broken case of the need to fallback. This adds a return type to a new interface member that lets the caller know it has to fallback. Fixes: 02c3dad0 ("Call shmget() with permission 0600 instead of 0777") Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> Part-of: <mesa/mesa!3823> (cherry picked from commit 466a0b2e)
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Dylan Baker authored
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