- Jun 11, 2023
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Equivalent of 284e6048 but for acceleration structure queries. If an app inserts a barrier between AS builds and writing AS properties, we must respect it or things will blow up. Cc: mesa-stable Reviewed-by:
Konstantin Seurer <konstantin.seurer@gmail.com> Part-of: <mesa/mesa!23568>
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radeonsi switched over to CU wavefront execution mode, but didn't tell LLVM. This can lead to shaders requiring too many VGPRs to be executed in CU mode and so cause GPU resets. Pass along +cumode to LLVM so it properly spills VGPRs. Fixes: 9d7eab2a ("radeonsi: don't enable WGP_MODE because of high cost of workgroup mem coherency") Signed-off-by:
Karol Herbst <git@karolherbst.de> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!23569>
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PIPE_FUNC_ -> COMPARE_FUNC_ pipe_compare_func -> compare_func Now include "pipe/p_state.h" is not needed and remove it in ac_nir.h Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Part-of: <mesa/mesa!23422>
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Martin Roukala authored
Valve infra is back online, sorry for the noise! This is a partial revert of commit 628d21c5. Signed-off-by:
Martin Roukala (né Peres) <martin.roukala@mupuf.org> Part-of: <mesa/mesa!23571>
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Fixes: e2dadda3 ("Revert "nir/lower_shader_calls: put inserted instructions into a dummy block") Closes: mesa/mesa#8978 Signed-off-by:
Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com> Reviewed-by:
Konstantin Seurer <konstantin.seurer@gmail.com> Part-of: <mesa/mesa!22884>
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Give bogus but meaningful names to the bitfields that we understand. Part-of: <!23467>
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- Jun 10, 2023
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Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!23567>
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Reviewed-by:
Karol Herbst <kherbst@redhat.com> Part-of: <!23544>
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PIPE_BIND_* belongs to gallium, do not use it in panvk As pan_format.h also used ban panfrost gallium driver, so static_assert it equal Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Reviewed-by:
Boris Brezillon <boris.brezillon@collabora.com> Part-of: <!23526>
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The uniform one is already set and the raygen shader isn't guarded anymore. Reviewed-by:
Friedrich Vock <friedrich.vock@gmx.de> Part-of: <mesa/mesa!23545>
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radv_nir_lower_rt_abi inserts instructions and control flow. Reviewed-by:
Friedrich Vock <friedrich.vock@gmx.de> Part-of: <mesa/mesa!23545>
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The condition will always evaluate to true because it's set this way by the prolog. Quake II RTX: Totals from 7 (10.00% of 70) affected shaders: Instrs: 30070 -> 30056 (-0.05%); split: -0.07%, +0.03% CodeSize: 163476 -> 163420 (-0.03%); split: -0.06%, +0.03% Latency: 80335 -> 83887 (+4.42%) InvThroughput: 16870 -> 17603 (+4.34%) Copies: 3191 -> 3215 (+0.75%) Branches: 1273 -> 1266 (-0.55%) PreSGPRs: 356 -> 354 (-0.56%) Reviewed-by:
Friedrich Vock <friedrich.vock@gmx.de> Part-of: <mesa/mesa!23545>
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This will be required for OpenCL subgroup support on radeonsi, but also fixes some regressions today as radeonsi started to use the subgroup id for invocation_index calculation. Fixes: 39da12b7 ("ac/llvm: clean up visit_load_local_invocation_index and visit_load_subgroup_id") Signed-off-by:
Karol Herbst <git@karolherbst.de> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!23551>
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Since radeonsi sets the alu_to_scalar callback, frontends like Rusticl might end up generating vec2 b2i16. Support this just like it's done for b2f16. Fixes: d692d433 ("radeonsi: use nir_lower_alu_to_scalar correctly") Signed-off-by:
Karol Herbst <git@karolherbst.de> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!23551>
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amdgpu enables gfxoff by default and the feature resets the RLC clock counter on idle on raven/raven2. Querying AMDGPU_INFO_TIMESTAMP does not work as expected on those platforms. There was an attempt in amdgpu to read from the TSC register instead, but it did not work without a firmware update[1]. Another possible solution is to disable the clock counter reset by clearing AMD_PG_SUPPORT_RLC_SMU_HS, but that causes a 0.2W increase of power consumption on idle which is undesirable. The clock counter reset affects vkCmdWriteTimestamp as well. The spec is vague on whether that is allowed or not. The WG is aware of the issue[2] but never really addresses it. [1] https://lists.freedesktop.org/archives/amd-gfx/2023-May/093731.html [2] https://github.com/KhronosGroup/Vulkan-Docs/issues/216 Part-of: <!23481>
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Fix defect reported by Coverity Scan. Missing unlock (LOCK) missing_unlock: Returning without unlocking drv->mutex. Fixes: af695149 ("frontends/va: pass in film_grain_target as new output") Signed-off-by:
Vinson Lee <vlee@freedesktop.org> Reviewed-by:
Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <mesa/mesa!23488>
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Fixes: 56eb8311 ("aco: run nir_lower_int64 after nir_opt_uniform_atomics") Signed-off-by:
Martin Roukala (né Peres) <martin.roukala@mupuf.org> Part-of: <mesa/mesa!23553>
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iris_disable_rhwo_optimization can only apply on gfxver 12.0, and has a version check to that affect. Add an assertion to warn us if the workaround ever applies to another version. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!21742>
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- Jun 09, 2023
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David Heidelberg authored
At this point is not needed anymore, remove it. Reviewed-by:
Guilherme Gallo <guilherme.gallo@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!23527>
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David Heidelberg authored
Reviewed-by:
Guilherme Gallo <guilherme.gallo@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <!23527>
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David Heidelberg authored
Since we use S3 artifacts for LAVA always, keep only one codepath. Reviewed-by:
Guilherme Gallo <guilherme.gallo@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!23527>
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David Heidelberg authored
Reviewed-by:
Guilherme Gallo <guilherme.gallo@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <!23527>
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David Heidelberg authored
Reviewed-by:
Guilherme Gallo <guilherme.gallo@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!23527>
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David Heidelberg authored
We don't use MINIO for a long time. Rename variable accordingly. Reviewed-by:
Guilherme Gallo <guilherme.gallo@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <!23527>
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David Heidelberg authored
Make the S3 (previously MINIO) artifacts clearly identifiable by glance. Also now we fail before compilation, if the job doesn't define the BUILDTYPE variable to prevent confusion. Reviewed-by:
Guilherme Gallo <guilherme.gallo@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!23527>
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David Heidelberg authored
Fail when a job gets introduced without build type. It should be explicitly stated what job uses. Reviewed-by:
Guilherme Gallo <guilherme.gallo@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <!23527>
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Adding `nir_rematerialize_derefs_in_use_blocks_impl` solves some cases when 'opt_dead_cf()' generates a phi instruction for the first argument of the `deref_store` intrinsic. Signed-off-by:
Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com> Closes: mesa/mesa#6742 Part-of: <mesa/mesa!22983>
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fixes: 521c216e closes: #9106 Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!23320>
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Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <mesa/mesa!23539>
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Part-of: <mesa/mesa!23468>
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Christian Gmeiner authored
The hardware doesn't support native conditional rendering, so it is implemented by software. Code borrowed from Freedreno and Panfrost. Signed-off-by:
Christian Gmeiner <cgmeiner@igalia.com> Reviewed-by:
Lucas Stach <l.stach@pengutronix.de> Part-of: <mesa/mesa!23392>
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Context flushes that are triggered by a pending write to the resource don't need to realize visibility of the resource changes outside of the context. Skip implicit resource flushes in those cases. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Christian Gmeiner <cgmeiner@igalia.com> Part-of: <mesa/mesa!23549>
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Avoids stack overflows with really large programs. No fossil-db changes. Closes: mesa/mesa#8760 Closes: mesa/mesa#8701 Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Cc: mesa-stable Part-of: <mesa/mesa!23531>
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Like our loads and stores, our global atomics support indexing with a 64-bit base plus a 32-bit element index, zero- or sign-extended and multiplied by the word size. Unlike the loads and stores, they do not support additional shifting (it's not too useful), so that needs an explicit lowering. Switch to using AGX variants of the atomics, running our address pattern matching on global atomics in order to delete some ALU. This cleans up the image atomic lowering nicely, since we get to take full advantage of the shift + zero-extend + add on the atomic... The shift comes from multiplying by the bytes per pixel. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <mesa/mesa!23529>
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So we can add more instructions without duplication. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <mesa/mesa!23529>
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This is a piece of cake with unified atomics :-) This will let us do our addressing math tricks nice and easily. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <mesa/mesa!23529>
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This is for producing (indirect) array register access. Since we don't handle that, this is a no-op. Drop the call, it's pointless and misleading. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Emma Anholt <emma@anholt.net> Part-of: <mesa/mesa!23529>
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This is for producing (indirect) array register access. Since we don't handle that, this is a no-op. Drop the call, it's pointless and misleading. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Erico Nunes <nunes.erico@gmail.com> Part-of: <mesa/mesa!23529>
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This is for producing (indirect) array register access. Since we don't handle that, this is a no-op. Drop the call, it's pointless and misleading. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by:
Italo Nicola <italonicola@collabora.com> Part-of: <mesa/mesa!23529>
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Signed-off-by:
Martin Roukala (né Peres) <martin.roukala@mupuf.org> Part-of: <mesa/mesa!23547>
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