Commit 43362991 authored by Rob Herring's avatar Rob Herring

drm/panfrost: rework gpu version handling and add hw issues

Signed-off-by: Rob Herring's avatarRob Herring <robh@kernel.org>
parent 7be0b5ac
......@@ -44,6 +44,7 @@ struct panfrost_features {
u32 js_features[16];
unsigned long base_hw_features[64 / BITS_PER_LONG];
unsigned long hw_issues[64 / BITS_PER_LONG];
};
struct panfrost_device {
......
/* SPDX-License-Identifier: GPL-2.0 */
/* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */
/* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
/* Copyright 2018 Panfrost Team */
#ifndef __PANFROST_FEATURES_H__
#define __PANFROST_FEATURES_H__
......@@ -43,20 +41,20 @@ enum base_hw_feature {
HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG,
};
#define hw_features_t60x (\
#define hw_features_t600 (\
BIT_ULL(HW_FEATURE_LD_ST_LEA_TEX) | \
BIT_ULL(HW_FEATURE_LINEAR_FILTER_FLOAT) | \
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
BIT_ULL(HW_FEATURE_V4))
#define hw_features_t62x (\
#define hw_features_t620 (\
BIT_ULL(HW_FEATURE_LD_ST_LEA_TEX) | \
BIT_ULL(HW_FEATURE_LINEAR_FILTER_FLOAT) | \
BIT_ULL(HW_FEATURE_ATTR_AUTO_TYPE_INFERRAL) | \
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
BIT_ULL(HW_FEATURE_V4))
#define hw_features_t72x (\
#define hw_features_t720 (\
BIT_ULL(HW_FEATURE_32_BIT_UNIFORM_ADDRESS) | \
BIT_ULL(HW_FEATURE_ATTR_AUTO_TYPE_INFERRAL) | \
BIT_ULL(HW_FEATURE_INTERPIPE_REG_ALIASING) | \
......@@ -68,7 +66,7 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_V4))
#define hw_features_t76x (\
#define hw_features_t760 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......@@ -86,7 +84,7 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT))
// T860
#define hw_features_tFxx (\
#define hw_features_t860 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......@@ -105,7 +103,9 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_TEST4_DATUM_MODE) | \
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT))
#define hw_features_t83x (\
#define hw_features_t880 hw_features_t860
#define hw_features_t830 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......@@ -125,7 +125,7 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_TEST4_DATUM_MODE) | \
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT))
#define hw_features_t82x (\
#define hw_features_t820 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......@@ -145,7 +145,7 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_TEST4_DATUM_MODE) | \
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT))
#define hw_features_tMIx (\
#define hw_features_g71 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......@@ -169,7 +169,7 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \
BIT_ULL(HW_FEATURE_COHERENCY_REG))
#define hw_features_tHEx (\
#define hw_features_g72 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......@@ -194,7 +194,7 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \
BIT_ULL(HW_FEATURE_COHERENCY_REG))
#define hw_features_tSIx (\
#define hw_features_g51 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......@@ -219,7 +219,7 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \
BIT_ULL(HW_FEATURE_COHERENCY_REG))
#define hw_features_tDVx (\
#define hw_features_g52 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......@@ -244,7 +244,7 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \
BIT_ULL(HW_FEATURE_COHERENCY_REG))
#define hw_features_tNOx (\
#define hw_features_g76 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......@@ -272,7 +272,7 @@ enum base_hw_feature {
BIT_ULL(HW_FEATURE_TLS_HASHING) | \
BIT_ULL(HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG))
#define hw_features_tGOx (\
#define hw_features_g31 (\
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
BIT_ULL(HW_FEATURE_XAFFINITY) | \
......
......@@ -6,6 +6,7 @@
#include "panfrost_device.h"
#include "panfrost_features.h"
#include "panfrost_issues.h"
#include "panfrost_gpu.h"
#include "panfrost_regs.h"
......@@ -263,11 +264,72 @@ static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
gpu_write(pfdev, GPU_JM_CONFIG, jm);
}
#define MAX_HW_REVS 6
struct panfrost_model {
const char *name;
u32 id;
u32 id_mask;
u64 features;
u64 issues;
struct {
u32 revision;
u64 issues;
} revs[MAX_HW_REVS];
};
#define GPU_MODEL(_name, _id, _mask, ...) \
{\
.name = __stringify(_name), \
.id = _id, \
.id_mask = _mask, \
.features = hw_features_##_name, \
.issues = hw_issues_##_name, \
.revs = { __VA_ARGS__ }, \
}
#define GPU_MODEL_MIDGARD(name, id, ...) GPU_MODEL(name, id, 0xfff, __VA_ARGS__)
#define GPU_MODEL_BIFROST(name, id, ...) GPU_MODEL(name, id, 0xf00f, __VA_ARGS__)
#define GPU_REV_EXT(name, _rev, _p, _s, stat) \
{\
.revision = (_rev) << 12 | (_p) << 4 | (_s), \
.issues = hw_issues_##name##_r##_rev##p##_p##stat, \
}
#define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, )
static const struct panfrost_model gpu_models[] = {
/* T60x has an oddball version */
GPU_MODEL(t600, 0x6956, 0xffff,
GPU_REV_EXT(t600, 0, 0, 1, _15dev0)),
GPU_MODEL_MIDGARD(t620, 0x620,
GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)),
GPU_MODEL_MIDGARD(t720, 0x720),
GPU_MODEL_MIDGARD(t760, 0x750,
GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1),
GPU_REV_EXT(t760, 0, 1, 0, _50rel0),
GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)),
GPU_MODEL_MIDGARD(t820, 0x820),
GPU_MODEL_MIDGARD(t830, 0x830),
GPU_MODEL_MIDGARD(t860, 0x860),
GPU_MODEL_MIDGARD(t880, 0x880),
GPU_MODEL_BIFROST(g71, 0x6000,
GPU_REV_EXT(g71, 0, 0, 1, _05dev0)),
GPU_MODEL_BIFROST(g72, 0x6001),
GPU_MODEL_BIFROST(g51, 0x7000),
GPU_MODEL_BIFROST(g76, 0x7001),
GPU_MODEL_BIFROST(g52, 0x7002),
GPU_MODEL_BIFROST(g31, 0x7003,
GPU_REV(g31, 1, 0)),
};
static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
{
u32 gpu_id, num_js, major, minor, status;
char *name = "unknown";
u32 gpu_id, num_js, major, minor, status, rev;
const char *name = "unknown";
u64 hw_feat = 0;
u64 hw_issues = hw_issues_all;
const struct panfrost_model *model;
int i;
pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES);
......@@ -306,77 +368,36 @@ static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
major = (pfdev->features.revision >> 12) & 0xf;
minor = (pfdev->features.revision >> 4) & 0xff;
status = pfdev->features.revision & 0xf;
rev = pfdev->features.revision;
gpu_id = pfdev->features.id;
if (gpu_id == 0x6956 || !(gpu_id & 0xf000)) {
switch (gpu_id) {
case 0x880:
hw_feat = hw_features_tFxx;
name = "mali-t880";
break;
case 0x860:
hw_feat = hw_features_tFxx;
name = "mali-t860";
break;
case 0x830:
hw_feat = hw_features_t83x;
name = "mali-t830";
break;
case 0x820:
hw_feat = hw_features_t82x;
name = "mali-t820";
break;
case 0x750:
hw_feat = hw_features_t76x;
name = "mali-t760";
break;
case 0x720:
hw_feat = hw_features_t72x;
name = "mali-t720";
break;
case 0x620:
hw_feat = hw_features_t62x;
name = "mali-t620";
break;
case 0x6956:
hw_feat = hw_features_t60x;
name = "mali-t600";
break;
}
} else {
/* Bifrost new style ID */
switch (gpu_id & 0xf00f) {
case 0x6000:
hw_feat = hw_features_tMIx;
name = "mali-g71";
break;
case 0x6001:
hw_feat = hw_features_tHEx;
name = "mali-g72";
break;
case 0x7000:
hw_feat = hw_features_tSIx;
name = "mali-g51";
break;
case 0x7001:
hw_feat = hw_features_tNOx;
name = "mali-g76";
break;
case 0x7002:
hw_feat = hw_features_tDVx;
name = "mali-g52";
break;
case 0x7003:
hw_feat = hw_features_tGOx;
name = "mali-g31";
for (model = gpu_models; model->name; model++) {
if ((gpu_id & model->id_mask) != model->id)
continue;
name = model->name;
hw_feat = model->features;
hw_issues |= model->issues;
for (i = 0; i < MAX_HW_REVS; i++) {
if ((model->revs[i].revision != rev) &&
(model->revs[i].revision != (rev & ~0xf)))
continue;
hw_issues |= model->revs[i].issues;
break;
}
break;
}
bitmap_from_u64(pfdev->features.base_hw_features, hw_feat);
bitmap_from_u64(pfdev->features.hw_issues, hw_issues);
dev_info(pfdev->dev, "%s id 0x%x major 0x%x minor 0x%x status 0x%x\n",
dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x",
name, gpu_id, major, minor, status);
dev_info(pfdev->dev, "features: %64pb, issues: %64pb",
pfdev->features.base_hw_features,
pfdev->features.hw_issues);
dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x",
gpu_read(pfdev, GPU_L2_FEATURES),
......
/* SPDX-License-Identifier: GPL-2.0 */
/* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */
/* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
#ifndef __PANFROST_ISSUES_H__
#define __PANFROST_ISSUES_H__
#include <linux/bitops.h>
#include "panfrost_device.h"
/*
* This is not a complete list of issues, but only the ones the driver needs
* to care about.
*/
enum base_hw_issue {
HW_ISSUE_6367,
HW_ISSUE_6787,
HW_ISSUE_8186,
HW_ISSUE_8245,
HW_ISSUE_8316,
HW_ISSUE_8394,
HW_ISSUE_8401,
HW_ISSUE_8408,
HW_ISSUE_8443,
HW_ISSUE_8987,
HW_ISSUE_9435,
HW_ISSUE_9510,
HW_ISSUE_9630,
HW_ISSUE_10327,
HW_ISSUE_10649,
HW_ISSUE_10676,
HW_ISSUE_10797,
HW_ISSUE_10817,
HW_ISSUE_10883,
HW_ISSUE_10959,
HW_ISSUE_10969,
HW_ISSUE_11020,
HW_ISSUE_11024,
HW_ISSUE_11035,
HW_ISSUE_11056,
HW_ISSUE_T76X_3542,
HW_ISSUE_T76X_3953,
HW_ISSUE_TMIX_8463,
GPUCORE_1619,
HW_ISSUE_TMIX_8438,
HW_ISSUE_TGOX_R1_1234,
HW_ISSUE_END
};
#define hw_issues_all (\
BIT_ULL(HW_ISSUE_9435))
#define hw_issues_t600 (\
BIT_ULL(HW_ISSUE_6367) | \
BIT_ULL(HW_ISSUE_6787) | \
BIT_ULL(HW_ISSUE_8408) | \
BIT_ULL(HW_ISSUE_9510) | \
BIT_ULL(HW_ISSUE_10649) | \
BIT_ULL(HW_ISSUE_10676) | \
BIT_ULL(HW_ISSUE_10883) | \
BIT_ULL(HW_ISSUE_11020) | \
BIT_ULL(HW_ISSUE_11035) | \
BIT_ULL(HW_ISSUE_11056) | \
BIT_ULL(HW_ISSUE_TMIX_8438))
#define hw_issues_t600_r0p0_15dev0 (\
BIT_ULL(HW_ISSUE_8186) | \
BIT_ULL(HW_ISSUE_8245) | \
BIT_ULL(HW_ISSUE_8316) | \
BIT_ULL(HW_ISSUE_8394) | \
BIT_ULL(HW_ISSUE_8401) | \
BIT_ULL(HW_ISSUE_8443) | \
BIT_ULL(HW_ISSUE_8987) | \
BIT_ULL(HW_ISSUE_9630) | \
BIT_ULL(HW_ISSUE_10969) | \
BIT_ULL(GPUCORE_1619))
#define hw_issues_t620 (\
BIT_ULL(HW_ISSUE_10649) | \
BIT_ULL(HW_ISSUE_10883) | \
BIT_ULL(HW_ISSUE_10959) | \
BIT_ULL(HW_ISSUE_11056) | \
BIT_ULL(HW_ISSUE_TMIX_8438))
#define hw_issues_t620_r0p1 (\
BIT_ULL(HW_ISSUE_10327) | \
BIT_ULL(HW_ISSUE_10676) | \
BIT_ULL(HW_ISSUE_10817) | \
BIT_ULL(HW_ISSUE_11020) | \
BIT_ULL(HW_ISSUE_11024) | \
BIT_ULL(HW_ISSUE_11035))
#define hw_issues_t620_r1p0 (\
BIT_ULL(HW_ISSUE_11020) | \
BIT_ULL(HW_ISSUE_11024))
#define hw_issues_t720 (\
BIT_ULL(HW_ISSUE_10649) | \
BIT_ULL(HW_ISSUE_10797) | \
BIT_ULL(HW_ISSUE_10883) | \
BIT_ULL(HW_ISSUE_11056) | \
BIT_ULL(HW_ISSUE_TMIX_8438))
#define hw_issues_t760 (\
BIT_ULL(HW_ISSUE_10883) | \
BIT_ULL(HW_ISSUE_T76X_3953) | \
BIT_ULL(HW_ISSUE_TMIX_8438))
#define hw_issues_t760_r0p0 (\
BIT_ULL(HW_ISSUE_11020) | \
BIT_ULL(HW_ISSUE_11024) | \
BIT_ULL(HW_ISSUE_T76X_3542))
#define hw_issues_t760_r0p1 (\
BIT_ULL(HW_ISSUE_11020) | \
BIT_ULL(HW_ISSUE_11024) | \
BIT_ULL(HW_ISSUE_T76X_3542))
#define hw_issues_t760_r0p1_50rel0 (\
BIT_ULL(HW_ISSUE_T76X_3542))
#define hw_issues_t760_r0p2 (\
BIT_ULL(HW_ISSUE_11020) | \
BIT_ULL(HW_ISSUE_11024) | \
BIT_ULL(HW_ISSUE_T76X_3542))
#define hw_issues_t760_r0p3 (\
BIT_ULL(HW_ISSUE_T76X_3542))
#define hw_issues_t820 (\
BIT_ULL(HW_ISSUE_10883) | \
BIT_ULL(HW_ISSUE_T76X_3953) | \
BIT_ULL(HW_ISSUE_TMIX_8438))
#define hw_issues_t830 (\
BIT_ULL(HW_ISSUE_10883) | \
BIT_ULL(HW_ISSUE_T76X_3953) | \
BIT_ULL(HW_ISSUE_TMIX_8438))
#define hw_issues_t860 (\
BIT_ULL(HW_ISSUE_10883) | \
BIT_ULL(HW_ISSUE_T76X_3953) | \
BIT_ULL(HW_ISSUE_TMIX_8438))
#define hw_issues_t880 (\
BIT_ULL(HW_ISSUE_10883) | \
BIT_ULL(HW_ISSUE_T76X_3953) | \
BIT_ULL(HW_ISSUE_TMIX_8438))
#define hw_issues_g31 0
#define hw_issues_g31_r1p0 (\
BIT_ULL(HW_ISSUE_TGOX_R1_1234))
#define hw_issues_g51 0
#define hw_issues_g52 0
#define hw_issues_g71 (\
BIT_ULL(HW_ISSUE_TMIX_8463) | \
BIT_ULL(HW_ISSUE_TMIX_8438))
#define hw_issues_g71_r0p0_05dev0 (\
BIT_ULL(HW_ISSUE_T76X_3953))
#define hw_issues_g72 0
#define hw_issues_g76 0
static inline bool panfrost_has_hw_issue(struct panfrost_device *pfdev, enum base_hw_issue feat)
{
return test_bit(feat, pfdev->features.hw_issues);
}
#endif /* _HWCONFIG_ISSUES_H_ */
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