- May 06, 2023
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David Heidelberg authored
Going from release candidate to stable kernel hopefully also improve overall stability. Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Part-of: <mesa/mesa!22873>
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This doesn't enable support for a7xx yet, but uses the new register pack builders for registers that differ between a7xx and a6xx. Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!22837>
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The open-coded flag param for "all the other bits" won't work once we have register variants in play. Signed-off-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!22837>
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Gert Wollny authored
Makes piglits related to texturequerylod and samplercubearray pass. Fixes: 79ca456b ("r600/sfn: rewrite NIR backend") Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <mesa/mesa!22883>
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Gert Wollny authored
Closes: mesa/mesa#8971 Fixes: 79ca456b ("r600/sfn: rewrite NIR backend") Signed-off-by:
Gert Wollny <gert.wollny@collabora.com> Part-of: <mesa/mesa!22883>
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- May 05, 2023
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Erik Faye-Lund authored
This renders a bit cleaner. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!21893>
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Erik Faye-Lund authored
We need to excape the underscores for shadow_ref, as well as escape non-math symbols. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!21893>
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Erik Faye-Lund authored
This block isn't valid latex, so let's just use a pseudocode-block like we do elsewhere here. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!21893>
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Erik Faye-Lund authored
These are math-blocks, which is supposed to use math-notation for conditionals. So let's change it to math notation. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!21893>
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Erik Faye-Lund authored
While we're at it, use some alignment so the equations still reads reasonably. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!21893>
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Erik Faye-Lund authored
It's better to split these two equations in two than to try to write extra text that needs lots of escaping. This fixes the LaTeX rendering to be somewhat readable. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!21893>
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Erik Faye-Lund authored
We need empty spaces here, otherwise LaTeX thinks it's one equation, and puts it all back onto one line. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!21893>
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Erik Faye-Lund authored
There's a mixture of indent styles here, with either two or three spaces. We have standardized on three spaces for .rst-files in the editorconfig, so let's apply that. While we're at it, make sure math-blocks are indented into their opcode-block. While the result might look the same most of the time, this matters when we have textual explaination following math-blocks, like we have in a few caess. If we don't indent the math there, we end up with having to unindent the text following the math-block for it not to count as a part of the math block, which looks very confusing when reading the source code. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!21893>
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Eric Engestrom authored
../src/microsoft/vulkan/dzn_image.c: In function ‘dzn_GetImageMemoryRequirements2’: ../src/microsoft/vulkan/dzn_image.c:918:91: error: passing argument 6 of ‘dzn_ID3D12Device12_GetResourceAllocationInfo3’ from incompatible pointer type [-Werror=incompatible-pointer-types] 918 | &image->castable_format_count, &image->castable_formats, | ^~~~~~~~~~~~~~~~~~~~~~~~ | | | DXGI_FORMAT ** In file included from ../src/microsoft/vulkan/dzn_private.h:67, from ../src/microsoft/vulkan/dzn_image.c:24: ../src/microsoft/vulkan/dzn_abi_helper.h:64:107: note: expected ‘const DXGI_FORMAT * const*’ but argument is of type ‘DXGI_FORMAT **’ 64 | const UINT *num_castable_formats, const DXGI_FORMAT *const *castable_formats, | ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~ cc1: some warnings being treated as errors ninja: build stopped: subcommand failed. Fixes: 71dbb312 ("dzn: Use GetResourceAllocationInfo3 for castable formats") Signed-off-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <mesa/mesa!22877>
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They haven't been seen since my fix landed. Part-of: <mesa/mesa!22863>
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Fixes: 2cbc24b9 ("turnip: fix buffer markers using wrong addresses") Part-of: <mesa/mesa!22863>
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10 flakes this month, starting with the noted job. Part-of: <mesa/mesa!22863>
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It no longer 100% crashes, but instead sometimes fails. Fixes: 91b06ea8 ("Uprev Piglit to 2391a83d1639a7ab7bbea02853b922878687b0e5") Part-of: <mesa/mesa!22863>
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Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <!22874>
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reason: in some cases, bs buffer size could cause assertion, and some bitstreams of certain resolutions could not be decoded. solution: to align the bs buffer to 128. fixes: 4f1646d7 Reviewed-by:
Boyuan Zhang <Boyuan.Zhang@amd.com> Signed-off-by:
Ruijing Dong <ruijing.dong@amd.com> Part-of: <mesa/mesa!22844>
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it's otherwise very annoying to figure out why this may or may not be available Part-of: <mesa/mesa!22854>
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this has the same requirements as GPL and then some Part-of: <mesa/mesa!22854>
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this is growing to be much larger than the original conditional Part-of: <mesa/mesa!22854>
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no functional changes Part-of: <mesa/mesa!22854>
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Lionel Landwerlin authored
Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Closes: mesa/mesa#8917 Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!22847>
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Lionel Landwerlin authored
We're about to manipulate these pools and dealing with the fix address ranges is painful. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!22847>
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Lionel Landwerlin authored
We want to add more heaps in the future and so not having to do address checks to find out in what heap to release a BO is convinient. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!22847>
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Lionel Landwerlin authored
Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!22847>
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Lionel Landwerlin authored
All the supported platforms should have 36+ bits of virtual address space. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Ivan Briano <ivan.briano@intel.com> Part-of: <mesa/mesa!22847>
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These asserts were checking isl_format_layout against itself, change to compare surface format layout against view format layout. Fixes: 628bfaf1 ("intel/isl: Add some sanity checks for compressed surfaces") Signed-off-by:
Tapani Pälli <tapani.palli@intel.com> Reviewed-by:
Nanley Chery <nanley.g.chery@intel.com> Part-of: <mesa/mesa!22790>
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- May 04, 2023
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Lionel Landwerlin authored
With the following test : dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.no_out_of_bounds_load There is a : shader_start: ... <- no control flow g0 = some_alu g1 = fbl g2 = broadcast g3, g1 g4 = get_buffer_size g2 ... <- no control flow halt <- on some lanes g5 = send <surface>, g4 eliminate_find_live_channel will remove the fbl/broadcast because it assumes lane0 is active at get_buffer_size : shader_start: ... <- no control flow g0 = some_alu g4 = get_buffer_size g0 ... <- no control flow halt <- on some lanes g5 = send <surface>, g4 But then the instruction scheduler will move the get_buffer_size after the halt : shader_start: ... <- no control flow halt <- on some lanes g0 = some_alu g4 = get_buffer_size g0 g5 = send <surface>, g4 get_buffer_size pulls the surface index from lane0 in g0 which could have been turned off by the halt and we end up accessing an invalid surface handle. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by:
Francisco Jerez <currojerez@riseup.net> Part-of: <mesa/mesa!20765>
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Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Qiang Yu <yuq825@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22690>
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There is no need to use alloc_vertices_and_primitives anymore, because it will be compiled to sendmsg anyway. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Qiang Yu <yuq825@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22690>
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Legacy GS needs to emit a DONE signal at the end. Do this in NIR instead of in the backends. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Qiang Yu <yuq825@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22690>
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Remove the GS intrinsics completely and emit the sendmsg here instead of in the backend. This is done to simplify backend code. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Qiang Yu <yuq825@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22690>
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Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Qiang Yu <yuq825@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22690>
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Will be used by ac/nir legacy and NGG lowerings. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Qiang Yu <yuq825@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22690>
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Contains a global wave ID of legacy GS waves. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Qiang Yu <yuq825@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22690>
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This intrinsic is going to be used for simplifying GS code. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Qiang Yu <yuq825@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!22690>
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Cc: mesa-stable Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Part-of: <mesa/mesa!22690>
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