radeonsi: Delete TCS epilogs entirely, and some cleanup.

Based on !28371 (merged) and !28408 (merged)

Remove the TCS epilog entirely from RadeonSI and ACO.

Refactor the bit fields in the TCS offchip layout SGPR so that there is room for the primitive type and whether TES reads tess factors; at the cost of calculating the patch data offset in the shader code. This barely affects TCS code generation because the TCS info already contains most of this information as constants, however it does add a few extra SALU instructions to TES.

Then, there are enough bits left in tcs_offchip_layout for adding the VS output count, thereby eliminating the need to have tessellation related info in the VS state SGPR, and also there is one more bit left that can be used to allow a higher number of patches to be processed per workgroup.