iris: More L3 cache flushing fixes

The first patch fixes an issue where HDC flushes were getting placed in separate PIPE_CONTROLs from other flushes for no good reason.

The second and third patches fix a regression in piglit.spec.arb_gl_spirv.execution.ssbo.unsized-array (#6314 (closed)) from my recent L3 series (!15275 (merged)) which appears to be due to the same SSBO existing in the L3 cache twice, tagged as Data$ and Tile$.

I have a fourth patch, not yet appearing in this MR, which tries to fix potential ordering issues with invalidates and flushes, but I haven't observed it to fix any actual bugs yet.