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radv: Optimize rt-pipeline traversal loop

Konstantin Seurer requested to merge KonstantinSeurer/mesa:rt-pipe into main

I added some optimizations I found while writing !14565 (merged) to the rt-pipeline traversal loop:

  • For some reason using an array as a stack is actually faster than shared memory.
  • I moved a bit of code into an if statement.

rx6700xt, Q2RTX: 26fps -> 28fps

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